--- title: A 64-bit, RVA23-compliant RISC-V core for... description: StarFive has launched Dubhe-100, a new 64-bit RVA23-compliant RISC-V CPU core designed for servers, HPC, and other high-performance applications. The core... canonical: https://daily.dev/posts/a-64-bit-rva23-compliant-risc-v-core-for-high-performance-applications-sqmndrlqb twitter:card: summary_large_image twitter:site: @dailydotdev og:type: website og:site_name: daily.dev og:title: A 64-bit, RVA23-compliant RISC-V core for high-performance applications | daily.dev og:description: StarFive has launched Dubhe-100, a new 64-bit RVA23-compliant RISC-V CPU core designed for servers, HPC, and other high-performance applications. The core... og:url: https://daily.dev/posts/a-64-bit-rva23-compliant-risc-v-core-for-high-performance-applications-sqmndrlqb og:image: https://api.daily.dev/og/posts/sqmnDrLqb.png og:image:alt: A 64-bit, RVA23-compliant RISC-V core for high-performance applications og:image:width: 1200 og:image:height: 630 og:locale: en --- > ## Documentation Index > Fetch the complete documentation index at: https://daily.dev/llms.txt > Use this file to discover all available pages before exploring further. # A 64-bit, RVA23-compliant RISC-V core for high-performance applications **[CNX Software](https://daily.dev/sources/cnx-software)** · [@cnxsoft](https://daily.dev/cnxsoft) · 3 min read · 2 upvotes · 0 comments ## Summary StarFive has launched Dubhe-100, a new 64-bit RVA23-compliant RISC-V CPU core designed for servers, HPC, and other high-performance applications. The core delivers a SPECint2006 score of 15/GHz, supports Vector and Vector Crypto extensions, and features a 15-stage pipeline with 6-wide issue, deep out-of-order execution, and multi-core cache coherence. It supports Sv39/Sv48 MMU modes, configurable PMP/PMA, and standard RISC-V debug and trace interfaces. Software development is supported via StarFive's StarStudio IDE with a Bare Metal SDK or a Linux SDK featuring Yocto and Linux Kernel 6.18, though SDKs aren't yet available for download. LECARC is among the first customers, building a server SoC around the core, with additional target markets including LLM inference, AI agents, computer vision, and infrastructure products like Smart NICs and storage controllers. ## Full article daily.dev links to this article rather than hosting it. Read it at the original source: ## Questions this post answers ### What is the SPECint2006 performance of the StarFive Dubhe-100 RISC-V core? The StarFive Dubhe-100 delivers a SPECint2006 score of 15 per GHz. It also achieves a Dhrystone v2.2 score of 10.0 per MHz (legal mode). The core uses a 15-stage pipeline with 6-wide issue, superscalar deep out-of-order execution, and implements the RV64GCBVH ISA with RVA23 compliance. _daily.dev helps chip engineers track new RISC-V core benchmarks like Dubhe-100 as they emerge._ ### Does the StarFive Dubhe-100 RISC-V core support vector instructions? Yes, the Dubhe-100 supports Vector and Vector Crypto extensions through a dedicated Vector Processing Unit. The VPU handles 8/16/32/64-bit integer and IEEE754-2008 16/32/64-bit floating-point plus BF16 operations, with VLEN equal to 2x DLEN (256 bits), two vector pipeline units, and two shared floating-point pipeline units. _engineers evaluating RISC-V cores for vector workloads can follow specs like this on daily.dev._ ### What SDKs are available for developing on the StarFive Dubhe-100 core? Development happens through StarFive's StarStudio IDE using either a Bare Metal SDK with GCC/LLVM toolchains, GDB, and pre-built OpenOCD, or a Linux SDK with Yocto, Linux Kernel 6.18, OpenSBI, and u-boot. Neither SDK is downloadable yet; they are expected to be released or updated on StarFive's GitHub once a commercial Dubhe-100 SoC ships. _developers planning RISC-V embedded toolchains can track SDK releases like these via daily.dev._ ## Similar posts on daily.dev - [Efinix Adds 64-Bit RISC-V SoC with Linux and DDR Support](https://daily.dev/posts/efinix-adds-64-bit-risc-v-soc-with-linux-and-ddr-support-1uedgwzr6) · Embedded.com · 0 upvotes · 0 comments - [Configurable RISC-V soft-cores with DDR3, LPDDR4x, and HyperRAM for Efinix FPGAs](https://daily.dev/posts/configurable-risc-v-soft-cores-with-ddr3-lpddr4x-and-hyperram-for-efinix-fpgas-xxjask61t) · CNX Software · 0 upvotes · 0 comments - [GCC 17 Compiler Lands SpacemiT X100 Core Targeting](https://daily.dev/posts/gcc-17-compiler-lands-spacemit-x100-core-targeting-21vwfvqan) · Phoronix · 0 upvotes · 0 comments --- Tags: [#linux](https://daily.dev/tags/linux), [#hardware](https://daily.dev/tags/hardware), [#embedded](https://daily.dev/tags/embedded) [View this post on daily.dev](https://daily.dev/posts/a-64-bit-rva23-compliant-risc-v-core-for-high-performance-applications-sqmndrlqb) ```json {"@context":"https://schema.org","@graph":[{"@type":"Organization","@id":"https://daily.dev/#organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180},"sameAs":["https://twitter.com/dailydotdev","https://github.com/dailydotdev","https://www.linkedin.com/company/daily-dev-ltd"]},{"@type":"WebSite","@id":"https://daily.dev/#website","url":"https://daily.dev","name":"daily.dev","publisher":{"@id":"https://daily.dev/#organization"},"potentialAction":{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https://daily.dev/search?q={search_term_string}"},"query-input":"required name=search_term_string"}}]} {"@context":"https://schema.org","@type":"TechArticle","headline":"A 64-bit, RVA23-compliant RISC-V core for high-performance applications","url":"https://daily.dev/posts/a-64-bit-rva23-compliant-risc-v-core-for-high-performance-applications-sqmndrlqb","mainEntityOfPage":{"@type":"WebPage","@id":"https://daily.dev/posts/a-64-bit-rva23-compliant-risc-v-core-for-high-performance-applications-sqmndrlqb"},"datePublished":"2026-08-20T00:02:04.788Z","dateModified":"2026-09-14T07:00:26.712Z","description":"StarFive has launched Dubhe-100, a new 64-bit RVA23-compliant RISC-V CPU core designed for servers, HPC, and other high-performance applications. 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It also achieves a Dhrystone v2.2 score of 10.0 per MHz (legal mode). The core uses a 15-stage pipeline with 6-wide issue, superscalar deep out-of-order execution, and implements the RV64GCBVH ISA with RVA23 compliance. daily.dev helps chip engineers track new RISC-V core benchmarks like Dubhe-100 as they emerge."}},{"@type":"Question","name":"Does the StarFive Dubhe-100 RISC-V core support vector instructions?","acceptedAnswer":{"@type":"Answer","text":"Yes, the Dubhe-100 supports Vector and Vector Crypto extensions through a dedicated Vector Processing Unit. The VPU handles 8/16/32/64-bit integer and IEEE754-2008 16/32/64-bit floating-point plus BF16 operations, with VLEN equal to 2x DLEN (256 bits), two vector pipeline units, and two shared floating-point pipeline units. engineers evaluating RISC-V cores for vector workloads can follow specs like this on daily.dev."}},{"@type":"Question","name":"What SDKs are available for developing on the StarFive Dubhe-100 core?","acceptedAnswer":{"@type":"Answer","text":"Development happens through StarFive's StarStudio IDE using either a Bare Metal SDK with GCC/LLVM toolchains, GDB, and pre-built OpenOCD, or a Linux SDK with Yocto, Linux Kernel 6.18, OpenSBI, and u-boot. Neither SDK is downloadable yet; they are expected to be released or updated on StarFive's GitHub once a commercial Dubhe-100 SoC ships. developers planning RISC-V embedded toolchains can track SDK releases like these via daily.dev."}}]} ```