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# AMD acquires Taalas to boost inference performance by etching models in silicon

**[Hacker News](https://daily.dev/sources/hn)** · 3 min read · 4 upvotes · 0 comments

## Summary

AMD has acquired AI chip startup Taalas, which specializes in etching AI models directly into silicon as model-specific integrated circuits. Early technology demonstrations show these custom chips achieving up to 17,000 tokens per second in inference performance, significantly boosting throughput compared to general-purpose accelerators.

## Full article

daily.dev links to this article rather than hosting it. Read it at the original source: <https://www.theregister.com/systems/2026/08/06/amd-acquires-ai-chip-startup-taalas-to-boost-inference-performance-by-etching-models-into-silicon/5284344>

## Questions this post answers

### What did AMD acquire Taalas for and what does it do?

AMD acquired AI chip startup Taalas to boost inference performance by etching trained models directly into silicon rather than running them on general-purpose processors. Early technical demos of these model-specific integrated circuits reportedly produced up to 17,000 tokens per second, a technique aimed at improving inference speed compared to conventional GPU-based approaches.

_Engineers weighing new inference hardware options can follow AMD's silicon-etched chip approach on daily.dev._

## Community take

How the wider developer community reacted, aggregated from 1 discussion and 160 comments across hackernews (as of 2026-09-14).

**TL;DR:** The community is genuinely excited by the speed demonstrated in the ChatJimmy demo, but deeply divided on whether baking models into silicon is a viable long-term strategy given the rapid pace of model development — with many arguing that for stable, "good enough" tasks the economics and performance gains are compelling.

**Sentiment:** 45% positive · 35% mixed · 20% skeptical

**The case for**

- The demo shows inference speeds roughly 30–90x faster than current cloud alternatives, which commenters found viscerally impressive.
- For tasks where current models are already capable enough, 100x speed gains are more impactful than chasing frontier capability.
- Etching models enables dramatically lower inference costs and power consumption, opening new use cases like always-on local agents.
- Models are surprisingly tolerant of imperfect weights, suggesting yield issues may not be a fatal flaw for this approach.
- A cartridge/daughterboard model could create a sustainable recurring revenue stream and bring trillion-parameter inference costs down to consumer peripheral pricing.

**The pushback**

- The pace of model development makes any silicon-baked model risk obsolescence within months of tape-out, with fabrication cycles of 6–24 months.
- The chips are physically large and not yet mobile-sized, limiting near-term deployment scenarios.
- The demo runs only an older Llama 3.1 8B model, which hallucinates and lacks depth — raising questions about whether the approach scales to frontier models.
- Architecture is still diverging, not converging, making it premature to commit a model to silicon.
- A small model already fits in cache and runs well in software, so the silicon advantage may not justify the cost for that tier.

**By community**

- hackernews (mixed): Broadly impressed by the raw speed demo but split on whether rapid model churn makes silicon-baked models a viable long-term bet versus a niche solution for stable, good-enough workloads.

**Hottest debate:** Whether the pace of AI model development makes etching models into silicon a brilliant cost/speed play for stable workloads or a fast track to expensive obsolescence.

**Open questions**

- What are the realistic fabrication turnaround times, and will a baked model always be too outdated by the time chips ship?
- How much of the performance gain comes from the weight-etching itself versus the large on-chip SRAM cache?
- At what model size does this approach become economically and physically feasible for mobile or consumer devices?
- How tolerant are larger, frontier-scale models to the yield defects inherent in very large custom ASICs?

**Highlights**

> At least in the case of Taalas the weights are physically encoded directly on the chip. It’s composed of 4-bit multiplier cells that compute all 16 possible results in parallel. The top metal wiring layer physically selects the one that corresponds to a multiplication with that cell’s constant weight, and route it to the next layer.
> — [foltik on hackernews](https://news.ycombinator.com/item?id=49203373)

> So this demo is around 90 times faster than typical speeds for the same model at openrouter, and around 30 times faster than the absolute fastest option available (Groq).
> — [dumberquestions on hackernews · 2 comments](https://news.ycombinator.com/item?id=49203053)

> It's a fantastic business opportunity to sell local models though. Sell a proprietary PCIe inference ASIC that accepts a ROM daughterboard holding a model. You don't actually need the compute of 8 flagship GPUs for inference. The name of the game has been the terabytes of memory. Move to an old node like 28nm and you sidestep supply chain issues and have a massively affordable product. Gut tells me you'd be able to turn a tidy margin selling those daughterboards at a couple hundred bucks. Update the model? Customers have to buy the new daughterboard, giving you a persistent income stream. Update the meta-architecture? You sell a new ASIC. Congratulations, you now dropped the capex for trillion-parameter models down from the price of a house, to the price of a normal computer peripheral.
> — [ux266478 on hackernews](https://news.ycombinator.com/item?id=49203320)

> My question is what changes about LLM use cases when you’re getting 1000 tok/s? Models in silicon might dramatically change how we think about them.
> — [teaearlgraycold on hackernews · 1 comments](https://news.ycombinator.com/item?id=49203581)

> AMD could have saved their money and used their own hardware! I've got a language model doing 60k tok/s on AMD hardware already, a Xilinx Kria K26 SOM, with the weights baked into URAM/BRAM with zero DRAM in the token loop. Same thesis as Taalas: single-stream decode is bandwidth bound, so stop fetching weights from far away. Caveats stacked high, obviously. It's 3.16M parameters (tinystories, and I also have a kevin-speak lemmatised version), the tokens are characters, and the 60k record is 16 streams that each remember exactly one token of context, so it's blisteringly fast at saying nothing. The honest build with full context and KV caching still does ~19k tok/s on one stream though. I keep messing with the blogpost with the live demo, but I'm planning on flipping it to live in the next day or two
> — [mikeayles on hackernews · 2 comments](https://news.ycombinator.com/item?id=49202697)

**Source threads**

- [hackernews](https://news.ycombinator.com/item?id=49201970) · 183 points · 160 comments

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---

Tags: [#gpu](https://daily.dev/tags/gpu), [#amd](https://daily.dev/tags/amd), [#ai-inference](https://daily.dev/tags/ai-inference)

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