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# AMD launches MI455X GPU and Helios rack platform, with Microsoft bringing both to Azure

**[Collections](https://daily.dev/sources/collections)** · 5 min read · 0 upvotes · 0 comments

## Summary

AMD has launched the Instinct MI455X GPU accelerator built on a 2nm process with 432GB of HBM4 memory, claiming up to 4x MXFP8/MXFP4 performance over the previous MI355X. Alongside it is the Helios rack-scale platform combining EPYC Venice CPUs, MI455X GPUs, and Pensando networking — delivering 4,600 CPU cores and 18,000 GPU compute units per rack. Shipments begin this quarter and ramp through Q4 into early 2027, with the MI500 and MI600 series on the roadmap for 2027 and 2028 respectively. Microsoft is integrating both into Azure via three new VM families: HDv2 for AI data processing and agentic workloads, HXv2 for EDA and large-scale MPI simulations, and ND MI455X v7 for production-scale AI inference and reasoning.

## Content

AMD held its Advancing AI 2026 event in San Francisco and came out swinging with new hardware, major customer commitments, and a surprisingly deep open-source push. Here's what was actually announced.

## The MI455X accelerator

The flagship chip is the Instinct MI455X, built on TSMC's 2nm process in a multi-chiplet package totaling 320 billion transistors. The compute dies use TSMC's GAA process while the fabric and cache dies use N3P.

The specs are genuinely impressive:

- 432GB of HBM4 memory at roughly 20TB/s bandwidth
- 40 petaflops of peak MXFP4 compute, 20 petaflops of MXFP8
- Up to 4x the MXFP8/MXFP4 performance of the previous MI355X

For context on the memory: Nvidia's Rubin pairs 288GB with each GPU. The MI455X carries 432GB, about 50% more. AMD is also finalizing a Samsung HBM4 supply contract; Lisa Su said the deal was nearly closed when asked about it at the event.

Architecturally, CDNA 5 makes a notable shift from Wave64 to native Wave32 execution. This reduces branch divergence penalties and register pressure, which matters for how efficiently compilers can map tensor workloads to hardware. AMD also added native hardware `tanh` instructions (useful for transformer activation functions like GeLU and SwiGLU), a dedicated Tensor Data Mover for asynchronous memory transfers, and replaced the large Infinity Cache with a 192MB shared global L2 cache.

The MI500 series is on track for 2027, MI600 for 2028.

## The Helios rack

Helios is AMD's rack-scale answer to Nvidia's NVL72 systems. One rack holds 72 Instinct MI455X GPUs and 18 EPYC Venice CPUs, with Pensando networking included in the same box. You buy compute by the rack.

The full rack delivers:

- 4,600 CPU cores and 18,000 GPU compute units
- Up to 31TB of HBM4 memory
- 2.9 FP4 exaflops of peak compute
- 1.8 TB/s per-GPU scale-up bandwidth via an all-to-all fabric

Networking is built on SONiC (open-source) and uses Broadcom Tomahawk 6 switches. AMD is aligning with UALink and Ultra Ethernet rather than Nvidia's proprietary NVLink, which gives hyperscalers a more modular path. Helios is in full production now, with shipments starting this quarter and ramping through Q4 and into H1 2027.

## Customer commitments

OpenAI, Meta, Oracle, Anthropic, and Microsoft all showed up. The headline deal is with Anthropic: AMD committed up to $10 billion in equity investment tied to milestones as Anthropic deploys up to 2 gigawatts of AMD compute via Helios systems starting H1 2027. A single Helios rack draws around 120kW, so 2 gigawatts works out to roughly 16,000 racks and over a million MI455X GPUs.

Microsoft is adding three new Azure VM families built around AMD hardware. HDv2 VMs feature nearly 500 EPYC 6th Gen cores, 4TB RAM, and 32TB NVMe for AI data processing. HXv2 VMs target EDA and scientific computing with 176 EPYC cores at 5+ GHz, 3D V-cache, and 800Gb InfiniBand. ND MI455X v7 VMs are powered by Helios and aimed at production-scale inference and reasoning workloads.

AMD also announced a partnership with Cerebras combining Helios racks with wafer-scale inference chips for ultra-low-latency workloads, set to ship in Q4.

## The software angle

The Anthropic partnership isn't just about buying racks. The two companies are collaborating on AMD's ROCm software stack, which has historically been AMD's weak point against CUDA. AMD launched Hyperloom, an open-source agentic system that uses Claude Code to profile workloads, identify bottlenecks, and rewrite GPU kernels from CUDA/C++ to HIP and Triton. Whether this actually closes the software gap with Nvidia remains to be seen, but it's a more concrete approach than AMD has taken before.

## The open-source push

Open hardware and open-source came up repeatedly throughout the event, more than you'd expect at a product launch:

- Kria AI Software Development Platform ships with open hardware schematics
- AMD Robotics Software Suite released as open-source, including RTL for the FPGA on the robotics developer kit
- Helios networking stack built on SONiC
- OpenBMC continues on new EPYC 9006 Venice server platforms
- OpenSIL is reaching production status on Zen 6, meaning open-source CPU silicon initialization is now a real thing in AMD's stack

## Venice-X and the market outlook

Lisa Su also introduced Venice-X, a data center CPU expected in 2027. AMD projected the AI accelerator market will reach $1.4 trillion by 2030, which would put it close to the size of today's entire semiconductor market.

## The stock reaction

Despite the announcements and the customer lineup, AMD shares fell around 4% on the day. The skepticism isn't hard to understand: Nvidia's Vera Rubin platform is already in full production and shipping to the same customers AMD just announced partnerships with. Benchmark comparisons between Helios and Vera Rubin are favorable for AMD on paper, but paper specs and production reality are different things. The Anthropic deal is large and real, but it doesn't start shipping until H1 2027. AMD has a history of strong hardware announcements that take time to translate into actual market share.

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