--- title: Attention Decode on AMD MI450 GPUs: A Gluon Kernel... description: A deep technical walkthrough of designing a high-performance attention decode kernel on AMD MI450 GPUs using Gluon, a Triton-based DSL. Covers four major... canonical: https://daily.dev/posts/attention-decode-on-amd-mi450-gpus-a-gluon-kernel-optimization-guide-xpcetmubd twitter:card: summary_large_image twitter:site: @dailydotdev og:type: website og:site_name: daily.dev og:title: Attention Decode on AMD MI450 GPUs: A Gluon Kernel Optimization Guide | daily.dev og:description: A deep technical walkthrough of designing a high-performance attention decode kernel on AMD MI450 GPUs using Gluon, a Triton-based DSL. Covers four major... og:url: https://daily.dev/posts/attention-decode-on-amd-mi450-gpus-a-gluon-kernel-optimization-guide-xpcetmubd og:image: https://api.daily.dev/og/posts/xpcETMUbd.png og:image:alt: Attention Decode on AMD MI450 GPUs: A Gluon Kernel Optimization Guide og:image:width: 1200 og:image:height: 630 og:locale: en --- > ## Documentation Index > Fetch the complete documentation index at: https://daily.dev/llms.txt > Use this file to discover all available pages before exploring further. # Attention Decode on AMD MI450 GPUs: A Gluon Kernel Optimization Guide **[Hacker News](https://daily.dev/sources/hn)** · 25 min read · 0 upvotes · 0 comments ## Summary A deep technical walkthrough of designing a high-performance attention decode kernel on AMD MI450 GPUs using Gluon, a Triton-based DSL. Covers four major optimizations: (1) tensor layout selection using AMDWMMALayout and DotOperandLayout for optimal WMMA instruction generation; (2) data loading via TDM (Tensor Data Mover) with descriptor-based bulk transfers bypassing cache for memory-bound workloads; (3) a four-stage software pipeline that interleaves TDM loads, LDS reads, QK/PV WMMA, and softmax vector ops with triple buffering to hide ~1000-cycle memory latency; and (4) Split-k parallelization using MI450 workgroup clusters to saturate all 256 WGPs. The optimized kernel achieves 85% of MI450's 19.6 TB/s peak HBM bandwidth (17.1 TB/s for GQA with H_kv=2). Full source code is open source in the Triton repository. ## Full article daily.dev links to this article rather than hosting it. Read it at the original source: ## Community take How the wider developer community reacted, aggregated from 1 discussion and 16 comments across hackernews (as of 2026-08-01). **TL;DR:** The Hacker News discussion largely ignores the technical content of the kernel optimization guide, instead debating AMD MI350 GPU availability, memory capacity limitations for large models like DeepSeek V4 Flash, and AMD's tendency to use proprietary jargon rather than aligning with NVIDIA's established terminology. **Sentiment:** 15% positive · 50% mixed · 35% skeptical **The pushback** - The MI350's 144GB VRAM is insufficient for frontier models like DeepSeek V4 Flash, which require 180GB+, potentially limiting its appeal. - AMD's use of proprietary jargon (instead of referencing equivalent NVIDIA/CUDA terms) adds friction for developers and contributes to ecosystem fragmentation. - MI350P is seen as a previous-generation, gimped PCIe SKU compared to the MI350X. **By community** - hackernews (mixed): Commenters largely sidestepped the technical kernel content to debate MI350 hardware availability, VRAM adequacy for large models, and AMD's jargon choices versus NVIDIA's established terminology. **Hottest debate:** Whether the AMD MI350's 144GB VRAM makes it dead on arrival for frontier model workloads like DeepSeek V4 Flash. **Open questions** - When will MI350/MI350P be available for purchase, and at what price point relative to NVIDIA's RTX PRO 6000? - Will AMD ever align its programming model terminology more closely with NVIDIA/CUDA to reduce developer friction? **Highlights** > As much as I enjoy these articles and for AMD to write more light technical articles, it really feels constrained, even strained, to be unable to cite the equivalent terms from the precursor here (NVIDIA). Another batch of jargon for very similar architectures and programming models... HIP and ROCm have actually made amazing strides in making CUDA developers' porting work easy, and I know playing catchup to a (monopolist) moving target you have no power over is bad... but I feel this is part of the thousand paper cuts. > — [touisteur on hackernews](https://news.ycombinator.com/item?id=49133847) > MI350 happens to not fit DeepSeek V4 Flash (144GB vs 180+ needed) so it will be dead on arrival. > — [lostmsu on hackernews · 2 comments](https://news.ycombinator.com/item?id=49133953) > This thing has 50% more memory than GTX PRO 6000, which fetch 18k-25k+ each right now on newegg, and generally sold out. If nvdia can still sell out 96GB PCI cards (on a 2 year old architecture) at those prices, how is an AMD equivalent with better specs dead on arrival? > — [tpurves on hackernews · 1 comments](https://news.ycombinator.com/item?id=49135728) **Source threads** - [hackernews](https://news.ycombinator.com/item?id=49077646) · 62 points · 16 comments ## Similar posts on daily.dev - [vLLM Triton Attention Backend Deep Dive](https://daily.dev/posts/vllm-triton-attention-backend-deep-dive-kx2nzacro) · vLLM · 0 upvotes · 0 comments - [Enabling vLLM V1 on AMD GPUs With Triton – PyTorch](https://daily.dev/posts/enabling-vllm-v1-on-amd-gpus-with-triton-pytorch-fmljwfltg) · PyTorch · 0 upvotes · 0 comments - [Systems Engineering Playbook: Optimizing Qwen 3.5-397B MoE on Ironwood \(TPU7x\)](https://daily.dev/posts/systems-engineering-playbook-optimizing-qwen-3-5-397b-moe-on-ironwood-tpu7x--quc6gr0fd) · Google Developers · 1 upvotes · 0 comments - [Efficient MoE Pre-training at Scale on 1K AMD GPUs with TorchTitan – PyTorch](https://daily.dev/posts/efficient-moe-pre-training-at-scale-on-1k-amd-gpus-with-torchtitan-pytorch-xscr4vica) · PyTorch · 0 upvotes · 0 comments - [Beyond Porting: How vLLM Orchestrates High-Performance Inference on AMD ROCm](https://daily.dev/posts/beyond-porting-how-vllm-orchestrates-high-performance-inference-on-amd-rocm-9sjfha0v1) · vLLM · 2 upvotes · 0 comments --- [View this post on daily.dev](https://daily.dev/posts/attention-decode-on-amd-mi450-gpus-a-gluon-kernel-optimization-guide-xpcetmubd) ```json {"@context":"https://schema.org","@graph":[{"@type":"Organization","@id":"https://daily.dev/#organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180},"sameAs":["https://twitter.com/dailydotdev","https://github.com/dailydotdev","https://www.linkedin.com/company/daily-dev-ltd"]},{"@type":"WebSite","@id":"https://daily.dev/#website","url":"https://daily.dev","name":"daily.dev","publisher":{"@id":"https://daily.dev/#organization"},"potentialAction":{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https://daily.dev/search?q={search_term_string}"},"query-input":"required name=search_term_string"}}]} {"@context":"https://schema.org","@type":"TechArticle","headline":"Attention Decode on AMD MI450 GPUs: A Gluon Kernel Optimization Guide","url":"https://daily.dev/posts/attention-decode-on-amd-mi450-gpus-a-gluon-kernel-optimization-guide-xpcetmubd","mainEntityOfPage":{"@type":"WebPage","@id":"https://daily.dev/posts/attention-decode-on-amd-mi450-gpus-a-gluon-kernel-optimization-guide-xpcetmubd"},"datePublished":"2026-08-01T15:08:14.095Z","dateModified":"2026-08-01T20:13:02.409Z","description":"A deep technical walkthrough of designing a high-performance attention decode kernel on AMD MI450 GPUs using Gluon, a Triton-based DSL. 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