A deep technical talk covering how modern multi-core hardware causes different CPU cores to have inconsistent views of memory. Topics include FIFO and coalescing write buffers, invalidate queues, multi-copy atomicity, out-of-order execution, and speculative execution. The talk then covers hardware solutions: memory fences (MFENCE, DSB, DMB on ARM), load-acquire and store-release instructions, and how Intel's lock-prefix atomic RMW operations differ from ARM's load-exclusive/store-exclusive (LDXR/STXR) mechanism. Finally, it maps these hardware concepts to C++11 memory order semantics (relaxed, acquire, release, seq_cst), explaining why understanding the hardware is essential for correctly using C++ atomics.
•48m watch time
1 Impression