--- title: Can you reverse engineer an ASIC? | daily.dev description: Jane Street has released a hardware puzzle challenging participants to reverse engineer an ASIC from its GDS layout file. Solvers must recover a netlist from... canonical: https://daily.dev/posts/can-you-reverse-engineer-an-asic--2gm3cxbzo copyright: © 2026 Daily Dev Ltd. terms: https://daily.dev/tos/ twitter:card: summary_large_image twitter:site: @dailydotdev og:type: website og:site_name: daily.dev og:title: Can you reverse engineer an ASIC? | daily.dev og:description: Jane Street has released a hardware puzzle challenging participants to reverse engineer an ASIC from its GDS layout file. Solvers must recover a netlist from... og:url: https://daily.dev/posts/can-you-reverse-engineer-an-asic--2gm3cxbzo og:image: https://api.daily.dev/og/posts/2gM3cXBZo.png og:image:alt: Can you reverse engineer an ASIC? og:image:width: 1200 og:image:height: 630 og:locale: en --- > ## Documentation Index > Fetch the complete documentation index at: https://daily.dev/llms.txt > Use this file to discover all available pages before exploring further. # Can you reverse engineer an ASIC? **[Hacker News](https://daily.dev/sources/hn)** · 5 min read · 0 upvotes · 0 comments ## Summary Jane Street has released a hardware puzzle challenging participants to reverse engineer an ASIC from its GDS layout file. Solvers must recover a netlist from the physical layout, determine the circuit's purpose, simulate it, and find a specific string output. A warm-up binary adder example with Verilog source, gate-level netlist, and GDS is provided, along with free open-source tools like KLayout and Magic VLSI. Submissions close September 4th, 2026. Jane Street also teases a follow-up competition where participants will design their own chips, with the best entries actually fabricated. ## Full article daily.dev links to this article rather than hosting it. Read it at the original source: ## Questions this post answers ### What tools can I use to open and inspect a GDS file for ASIC reverse engineering? KLayout and Magic VLSI are two free, open-source tools that can open GDS files and let you inspect the individual routing and transistor layers. The Jane Street ASIC puzzle uses an open-source PDK, so both tools work with the provided layout files without any proprietary dependencies. _Hardware engineers exploring chip-level tooling find the latest GDS tooling discussions on daily.dev._ ## Community take How the wider developer community reacted, aggregated from 1 discussion and 100 comments across hackernews (as of 2026-08-07). **TL;DR:** Commenters find the Jane Street ASIC reverse-engineering puzzle genuinely interesting and tractable, with several noting that extracting a gate-level netlist from a GDS is routine with standard EDA tools — the real challenge is recovering the circuit's higher-level function. A lively side-thread debates whether a retold story of oscilloscope-based GPU reverse engineering is plausible (consensus: no). **Sentiment:** 55% positive · 30% mixed · 15% skeptical **The case for** - Getting a logic-gate netlist from a GDS is a well-understood, daily workflow for chip designers using tools like Calibre, making the puzzle approachable for those with EDA access. - Standard-cell designs are far more readable than hand-optimized chips like the 6502, lowering the barrier for participants. - The puzzle is seen as a clever (if thinly veiled) recruiting exercise, which commenters find amusing rather than off-putting. - Real-world precedents exist — CTF teams have solved similar hardware reverse-engineering challenges before. **The pushback** - The puzzle likely requires access to expensive industry EDA tools (Cadence, Synopsys, Mentor) that most hobbyists don't have. - The warm-up GDS apparently wasn't flattened, making the hierarchy trivially recoverable and reducing its value as a challenge preview. - The hardest part — inferring the circuit's purpose from a recovered netlist — is not addressed by any tooling and remains a significant open problem. **By community** - hackernews (positive): Broadly enthusiastic, with knowledgeable chip designers explaining the toolchain and debating the difficulty, plus a long tangential thread fact-checking an implausible GPU reverse-engineering anecdote. **Hottest debate:** Whether the retold story of a postdoc reverse-engineering an NVIDIA GPU by connecting oscilloscopes and applying random inputs is physically plausible — experts strongly say no, while others argue the details were simply garbled in retelling. **Open questions** - What tools are realistically available to non-industry participants without access to Cadence/Synopsys/Mentor licenses? - Will Jane Street publish a writeup or solution after the September 4th deadline, as they apparently didn't for their previous neural-net challenge? - How difficult is the 'netlist-to-function' step once the gate-level netlist is recovered? **Highlights** > Getting a logic-gate-level netlist from a GDS is trivial with industry standard chip design tools. Circuit designers do this every day. The hardest part will be reverse engineering the functionality. I wish I had more time and I'd throw Calibre at it. > — [kayson on hackernews · 2 comments](https://news.ycombinator.com/item?id=49204079) > Indeed, this is a problem for an energetic student who has free access to every tool in the Cadence, Synopsys, and Mentor portfolios: take the GDS-II layout, run it through extraction, generate a netlist, convert to higher-level blocks ("netlist-to-gate recovery"), translate to RTL HDL, then attempt to work out "what it does." This is just a job posting in disguise for Jane Street: solve the puzzle, get a call from one of their recruiters. > — [roadbuster on hackernews](https://news.ycombinator.com/item?id=49205041) > I'm a chip designer, back in the early 90s I visited a small silicon house who were doing some work for us, their boardroom table had been taken over by a giant sized photomicrograph of IBM's VGA chip and they had a bunch of summer hire grad students tracing wiring and matching standard cells (easier back then because we only worked in 2 layers of metal). They weren't trying to steal IBM's design, they already had one of their own, what they wanted to know was "is there any as yet unannounced functionality in the IBM VGA chip?" they didn't want to be caught out when some unknown registers popped up. Of course it turned out there was as yet unannounced functionality - but not by IBM's design, more because of the orthogonality of the design - MODE-X was discovered and became the basis for DOOM's speed, anyone who didn't support it lost out > — [Taniwha on hackernews · 1 comments](https://news.ycombinator.com/item?id=49204457) > There is absolutely no way that happened. 15 years ago, we're talking Fermi class GPUs and chips with hundreds of millions of bits of on-chip state and much more if you include the DRAM. You can't tease out the right information by applying random inputs. Which input would you even use? The PCIe interface? You'd first "randomly" need to get past its complex training sequences... Your postdoc probably wrote micro-benchmarks of some sort. That is a common technique. > — [tverbeure on hackernews · 2 comments](https://news.ycombinator.com/item?id=49203405) > In a simplified scenario (not too far from this)? Yeah, we've done that in CTFs almost a decade ago. https://blog.dragonsector.pl/2017/10/?m=1 > — [q3k on hackernews · 1 comments](https://news.ycombinator.com/item?id=49202794) **Source threads** - [hackernews](https://news.ycombinator.com/item?id=49200933) · 60 points · 100 comments ## Similar posts on daily.dev - [Can you reverse engineer our neural network?](https://daily.dev/posts/can-you-reverse-engineer-our-neural-network--8zx43hq0j) · Hacker News · 0 upvotes · 0 comments - [The FPGA Chronicles: Ready To Probe](https://daily.dev/posts/the-fpga-chronicles-ready-to-probe-m1apwkauf) · Hackaday · 0 upvotes · 0 comments - [Pure Silicon Demo Coding: No CPU, No Memory, Just 4k Gates](https://daily.dev/posts/pure-silicon-demo-coding-no-cpu-no-memory-just-4k-gates-erfarcxe9) · Hacker News · 3 upvotes · 0 comments - [How OpenAI Used Its Own LLMs to Design Its Jalapeño Chip](https://daily.dev/posts/how-openai-used-its-own-llms-to-design-its-jalape-o-chip-kiphvnkd0) · IEEE Spectrum · 1 upvotes · 0 comments --- Tags: [#hardware](https://daily.dev/tags/hardware), [#reverse-engineering](https://daily.dev/tags/reverse-engineering), [#fpga](https://daily.dev/tags/fpga) [View this post on daily.dev](https://daily.dev/posts/can-you-reverse-engineer-an-asic--2gm3cxbzo) ```json {"@context":"https://schema.org","@graph":[{"@type":"Organization","@id":"https://daily.dev/#organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180},"sameAs":["https://twitter.com/dailydotdev","https://github.com/dailydotdev","https://www.linkedin.com/company/daily-dev-ltd"]},{"@type":"WebSite","@id":"https://daily.dev/#website","url":"https://daily.dev","name":"daily.dev","publisher":{"@id":"https://daily.dev/#organization"},"potentialAction":{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https://daily.dev/search?q={search_term_string}"},"query-input":"required name=search_term_string"}}]} {"@context":"https://schema.org","@type":"TechArticle","headline":"Can you reverse engineer an ASIC?","url":"https://daily.dev/posts/can-you-reverse-engineer-an-asic--2gm3cxbzo","mainEntityOfPage":{"@type":"WebPage","@id":"https://daily.dev/posts/can-you-reverse-engineer-an-asic--2gm3cxbzo"},"datePublished":"2026-08-06T22:01:27.894Z","dateModified":"2026-08-07T11:36:33.286Z","description":"Jane Street has released a hardware puzzle challenging participants to reverse engineer an ASIC from its GDS layout file. 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