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title: Cerebras Deploys Trillion-Parameter AI Models | daily.dev
description: Cerebras explains how it splits trillion-parameter models across multiple WSE-3T wafers to serve inference at 1,000 to 2,000+ tokens per second. Using the...
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# Cerebras Deploys Trillion-Parameter AI Models

**[Hacker News](https://daily.dev/sources/hn)** · 6 min read · 3 upvotes · 0 comments

## Summary

Cerebras explains how it splits trillion-parameter models across multiple WSE-3T wafers to serve inference at 1,000 to 2,000+ tokens per second. Using the open-source 3-trillion-parameter Kimi K3 model as an example, each layer needs about 16GB at 4-bit quantization, requiring 59 wafers total (one per dense layer, two linear-attention layers per wafer). Wafers connect in a pipeline, passing only activations between them over RDMA at roughly 2 microseconds per hop. Multiple requests fill the pipeline concurrently, and on-chip KV cache space sets the ceiling on how many requests can run at once.

## Full article

daily.dev links to this article rather than hosting it. Read it at the original source: <https://www.cerebras.ai/blog/how-we-deploy-trillion-parameter-frontier-models-on-cerebras>

## Questions this post answers

### How many Cerebras WSE-3T wafers are needed to run a 3 trillion parameter model like Kimi K3?

Fifty-nine wafers. With 4-bit weight quantization, each of Kimi K3's 93 layers needs about 16GB. Dense layers (24 of them) each get their own wafer to leave room for KV cache, needing 24 wafers, while linear-attention layers (69 of them) fit two per 44GB wafer, needing 35 wafers, for a total of 59.

_Anyone scoping multi-chip inference hardware can track real-world deployment math like this on daily.dev._

### What data moves between Cerebras wafers when running a pipelined LLM inference across chips?

Only activations move between wafers, not model weights. Because each wafer has 44GB of on-chip SRAM and each layer is only about 16GB, entire layers typically fit directly on a single chip, so weights never need to move. Activations are passed between wafers via RDMA over Ethernet at roughly 2 microseconds per hop.

_Engineers weighing wafer-scale versus GPU inference architectures can follow details like this on daily.dev._

### Why do dense attention layers need more on-chip memory than linear-attention layers during LLM inference?

Dense (full-attention) layers must store a KV cache holding keys and values for every token in every active request, so they need extra room on their wafer. Linear-attention layers instead keep a small, fixed-size state per request regardless of context length, so two linear layers can share one 44GB wafer instead of just one dense layer.

_Developers reasoning about attention mechanism memory tradeoffs can dig into examples like this on daily.dev._

## Community take

How the wider developer community reacted, aggregated from 2 discussions and 59 comments across hackernews (as of 2026-10-25).

**TL;DR:** Discussion centers on the technical architecture (wafer tiling, pipeline vs. GPU-style parallelism, SRAM capacity) with genuine curiosity, alongside skepticism about Cerebras's real-world model quality, availability, and business position compared to Nvidia-based offerings.

**Sentiment:** 20% positive · 45% mixed · 35% skeptical

**The case for**

- Extremely high token throughput could change how people iterate with LLMs, enabling near-compiler-like rebuild workflows.
- The architecture explanation (pipeline parallelism across wafers, weights-stationary/activations-flow design) was seen as a genuinely interesting technical approach.
- Some note strong enterprise demand suggests the company may be doing something right despite the skepticism.

**The pushback**

- Available models on the platform (e.g. GPT-OSS 120b, Qwen variants) are seen as weak or 'mostly wrong' despite the speed.
- Claims about ultrafast GPT models running on Cerebras hardware were disputed; several commenters say those actually run on Nvidia.
- High speed doesn't help if batching/concurrency benefits don't pass through to the end user, who still pays per token.
- Doubts that raw speed matters much given quality/maintainability concerns with LLM-generated code.
- Pricing and real-world speed often don't match the advertised 1000-2000 tokens/sec, especially via routers.
- One comparison calls the company the 'Transmeta of the AI wave', implying skepticism about long-term viability.

**By community**

- hackernews (mixed): A deep technical sub-thread admires the wafer/pipeline architecture while a parallel thread is skeptical about model quality, availability, and whether the speed advantage is overstated.

**Hottest debate:** Whether Cerebras's headline speed/business claims (e.g. which models truly run on their hardware, and whether users actually benefit from pipeline concurrency) are real or overstated.

**Open questions**

- Why exactly does GPU-based batching differ from the pipeline concurrency described here — is it a hardware limitation or just missing software scaffolding?
- How is KV cache managed/fetched for many concurrent requests when it exceeds on-chip SRAM capacity?
- Why do chip layouts universally use square/rectangular grids rather than hexagonal or diagonal topologies?

**Highlights**

> That has never been made available even to limited customers as far as reporting goes. Currently available ultrafast on GPT-6 Astra and GPT-6.1 Sol are all using Nvidia for good reason [0]. The fact that Cerebras, which has a willing and major customer like OpenAI begging at their heels to deploy on their hardware, now posts about a 2.8T open weight model says a lot. [0] https://blogs.nvidia.com/blog/gpus-openai-gpt-6-astra-ultraf...
> — [Topfi on hackernews · 1 comments](https://news.ycombinator.com/item?id=50229580)

> Cerebras is good on paper but all I can reasonably access is "GPT OSS 120b, Qwen 3.8 27B" which aren't very good for my use. Openrouter on nitro gets me there. Although the TPS is 5X less still. I have tried GPT OSS 120b on cerebras and it flies. But it's mostly wrong.
> — [keyle on hackernews · 2 comments](https://news.ycombinator.com/item?id=50228806)

> The reason 2D grids work well is because you can split tensor axes along whatever dim you want across PEs (batch, sequence, hidden, etc.). And your per PE code is relatively simple. It's of the type : get data from neighbor, compute my subtensor, send to neighbor. And you can implement broadcasts and reduces along any axis.
> — [bubblethink on hackernews](https://news.ycombinator.com/item?id=50228296)

> It's describing a different type of parallelism - pipeline parallelism. The network is laid out spatially on the wafer in CB's case. So weights are stationary and activations flow. A GPU is going to process the network one layer at a time. GPUs also use other types of parallelism (tensor and expert mainly in inference). Pipeline parallelism doesn't make much sense on a GPU for inference.
> — [bubblethink on hackernews · 1 comments](https://news.ycombinator.com/item?id=50228436)

> And the fact that you will never be benefited from the batching they’ve explained either, you’ll be paying for every token sequential or parallel unlike nvidia or amd gpus
> — [villgax on hackernews](https://news.ycombinator.com/item?id=50229178)

**Source threads**

- [hackernews](https://news.ycombinator.com/item?id=50227356) · 161 points · 59 comments
- [hackernews](https://news.ycombinator.com/item?id=50202098) · 2 points · 0 comments

## Similar posts on daily.dev

- [OpenAI to serve ChatGPT on Cerebras' AI dinner plates](https://daily.dev/posts/openai-to-serve-chatgpt-on-cerebras-ai-dinner-plates-2gruqttfd) · The Register · 0 upvotes · 0 comments
- [How to serve trillions of tokens for trillion-parameter coding agents](https://daily.dev/posts/how-to-serve-trillions-of-tokens-for-trillion-parameter-coding-agents-mdxlvkzhk) · Modal · 0 upvotes · 0 comments

---

Tags: [#ai-inference](https://daily.dev/tags/ai-inference), [#cerebras](https://daily.dev/tags/cerebras)

[View this post on daily.dev](https://daily.dev/posts/cerebras-deploys-trillion-parameter-ai-models-b98xhzcwd)

```json
{"@context":"https://schema.org","@graph":[{"@type":"Organization","@id":"https://daily.dev/#organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180},"sameAs":["https://twitter.com/dailydotdev","https://github.com/dailydotdev","https://www.linkedin.com/company/daily-dev-ltd"]},{"@type":"WebSite","@id":"https://daily.dev/#website","url":"https://daily.dev","name":"daily.dev","publisher":{"@id":"https://daily.dev/#organization"},"potentialAction":{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https://daily.dev/search?q={search_term_string}"},"query-input":"required name=search_term_string"}}]}
{"@context":"https://schema.org","@type":"TechArticle","headline":"Cerebras Deploys Trillion-Parameter AI Models","url":"https://daily.dev/posts/cerebras-deploys-trillion-parameter-ai-models-b98xhzcwd","mainEntityOfPage":{"@type":"WebPage","@id":"https://daily.dev/posts/cerebras-deploys-trillion-parameter-ai-models-b98xhzcwd"},"datePublished":"2026-10-25T04:48:49.418Z","dateModified":"2026-10-25T10:05:02.399Z","description":"Cerebras explains how it splits trillion-parameter models across multiple WSE-3T wafers to serve inference at 1,000 to 2,000+ tokens per second. Using the...","image":"https://media.daily.dev/image/upload/f_auto,q_auto/v1/posts/9ea1927c5f630ef01aec82315b50af16?_a=AQAEuop","thumbnailUrl":"https://media.daily.dev/image/upload/f_auto,q_auto/v1/posts/9ea1927c5f630ef01aec82315b50af16?_a=AQAEuop","isAccessibleForFree":true,"articleSection":"Hacker News","inLanguage":"en","publisher":{"@type":"Organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180}},"author":{"@type":"Organization","name":"Hacker News","logo":"https://media.daily.dev/image/upload/t_logo,f_auto/v1/logos/hn","url":"https://daily.dev/sources/hn"},"commentCount":0,"discussionUrl":"https://daily.dev/posts/cerebras-deploys-trillion-parameter-ai-models-b98xhzcwd","interactionStatistic":[{"@type":"InteractionCounter","interactionType":{"@type":"LikeAction"},"userInteractionCount":3},{"@type":"InteractionCounter","interactionType":{"@type":"CommentAction"},"userInteractionCount":0}],"keywords":"ai-inference,cerebras","timeRequired":"PT6M"}
{"@context":"https://schema.org","@type":"BreadcrumbList","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https://daily.dev"},{"@type":"ListItem","position":2,"name":"Hacker News","item":"https://daily.dev/sources/hn"},{"@type":"ListItem","position":3,"name":"Cerebras Deploys Trillion-Parameter AI Models"}]}
{"@context":"https://schema.org","@type":"FAQPage","@id":"https://daily.dev/posts/cerebras-deploys-trillion-parameter-ai-models-b98xhzcwd#faq","mainEntity":[{"@type":"Question","name":"How many Cerebras WSE-3T wafers are needed to run a 3 trillion parameter model like Kimi K3?","acceptedAnswer":{"@type":"Answer","text":"Fifty-nine wafers. With 4-bit weight quantization, each of Kimi K3's 93 layers needs about 16GB. Dense layers (24 of them) each get their own wafer to leave room for KV cache, needing 24 wafers, while linear-attention layers (69 of them) fit two per 44GB wafer, needing 35 wafers, for a total of 59. Anyone scoping multi-chip inference hardware can track real-world deployment math like this on daily.dev."}},{"@type":"Question","name":"What data moves between Cerebras wafers when running a pipelined LLM inference across chips?","acceptedAnswer":{"@type":"Answer","text":"Only activations move between wafers, not model weights. Because each wafer has 44GB of on-chip SRAM and each layer is only about 16GB, entire layers typically fit directly on a single chip, so weights never need to move. Activations are passed between wafers via RDMA over Ethernet at roughly 2 microseconds per hop. Engineers weighing wafer-scale versus GPU inference architectures can follow details like this on daily.dev."}},{"@type":"Question","name":"Why do dense attention layers need more on-chip memory than linear-attention layers during LLM inference?","acceptedAnswer":{"@type":"Answer","text":"Dense (full-attention) layers must store a KV cache holding keys and values for every token in every active request, so they need extra room on their wafer. Linear-attention layers instead keep a small, fixed-size state per request regardless of context length, so two linear layers can share one 44GB wafer instead of just one dense layer. Developers reasoning about attention mechanism memory tradeoffs can dig into examples like this on daily.dev."}}]}
```

