ARM Cortex-M interrupt priorities are notoriously confusing due to inverted numbering (lower number = higher urgency), MSB-aligned priority bits in NVIC registers, and inconsistent conventions across CMSIS functions. Key points covered: NVIC priority registers store bits in the most-significant positions, requiring bit-shifting when writing directly; CMSIS NVIC_SetPriority() handles the shift internally so values must NOT be pre-shifted; preempt priority vs. subpriority grouping and why all bits should default to preempt priority; and the difference between PRIMASK (disables all interrupts) and BASEPRI (selectively disables by urgency level). Notably, __set_BASEPRI() uses the hardware convention requiring manual bit-shifting, unlike NVIC_SetPriority().
