--- title: "Cutting Through the Confusion with ARM Cortex-M Interrupt Priorities" url: https://daily.dev/posts/cutting-through-the-confusion-with-arm-cortex-m-interrupt-priorities-xtteots2m source_url: https://www.embeddedrelated.com/showarticle/923.php type: article source: "EmbeddedRelated" published: 2026-05-31T07:48:25.639Z updated: 2026-05-31T09:20:01.544Z tags: ["embedded", "real-time-systems"] reading_time: 7 upvotes: 0 comments: 0 language: en --- > ## Documentation Index > Fetch the complete documentation index at: https://daily.dev/llms.txt > Use this file to discover all available pages before exploring further. # Cutting Through the Confusion with ARM Cortex-M Interrupt Priorities **[EmbeddedRelated](https://daily.dev/sources/embeddedrelated)** · 7 min read · 0 upvotes · 0 comments ## Summary ARM Cortex-M interrupt priorities are notoriously confusing due to inverted numbering (lower number = higher urgency), MSB-aligned priority bits in NVIC registers, and inconsistent conventions across CMSIS functions. Key points covered: NVIC priority registers store bits in the most-significant positions, requiring bit-shifting when writing directly; CMSIS NVIC_SetPriority() handles the shift internally so values must NOT be pre-shifted; preempt priority vs. subpriority grouping and why all bits should default to preempt priority; and the difference between PRIMASK (disables all interrupts) and BASEPRI (selectively disables by urgency level). Notably, __set_BASEPRI() uses the hardware convention requiring manual bit-shifting, unlike NVIC_SetPriority(). ## Full article daily.dev links to this article rather than hosting it. Read it at the original source: --- Tags: [#embedded](https://daily.dev/tags/embedded), [#real-time-systems](https://daily.dev/tags/real-time-systems) [View this post on daily.dev](https://daily.dev/posts/cutting-through-the-confusion-with-arm-cortex-m-interrupt-priorities-xtteots2m)