--- title: Dynamic MAC Learning: Hardware or CPU Activity? «... description: Dynamic MAC learning in hardware switches is more nuanced than commonly assumed. Rather than a simple hardware-vs-CPU binary, most modern ASICs support both:... canonical: https://daily.dev/posts/dynamic-mac-learning-hardware-or-cpu-activity-ipspace-net-blog-bzdxn9vzw twitter:card: summary_large_image twitter:site: @dailydotdev og:type: website og:site_name: daily.dev og:title: Dynamic MAC Learning: Hardware or CPU Activity? « ipSpace.net blog | daily.dev og:description: Dynamic MAC learning in hardware switches is more nuanced than commonly assumed. Rather than a simple hardware-vs-CPU binary, most modern ASICs support both:... og:url: https://daily.dev/posts/dynamic-mac-learning-hardware-or-cpu-activity-ipspace-net-blog-bzdxn9vzw og:image: https://api.daily.dev/og/posts/bZdxn9vzw.png og:image:alt: Dynamic MAC Learning: Hardware or CPU Activity? « ipSpace.net blog og:image:width: 1200 og:image:height: 630 og:locale: en --- > ## Documentation Index > Fetch the complete documentation index at: https://daily.dev/llms.txt > Use this file to discover all available pages before exploring further. # Dynamic MAC Learning: Hardware or CPU Activity? « ipSpace.net blog **[ipSpace.net Blog](https://daily.dev/sources/ipspace)** · 5 min read · 0 upvotes · 0 comments ## Summary Dynamic MAC learning in hardware switches is more nuanced than commonly assumed. Rather than a simple hardware-vs-CPU binary, most modern ASICs support both: hardware can autonomously update MAC hash tables, but hash collision handling (e.g., cuckoo hashing) is complex enough that many implementations offload it to a CPU — either one embedded in the ASIC or the main NOS CPU. Broadcom ASICs, for example, offer configurable 'CPU managed learning' modes. In multi-ASIC or chassis environments, the NOS CPU gets involved regardless to propagate MAC entries across all ASICs. EVPN's BGP-based MAC learning is contrasted with this traditional approach, where a L2manager communicates with L2RIB/BGP to distribute RT-2 routes. The post synthesizes community input from FPGA designers, ASIC engineers, and networking experts, including a pointer to the public Broadcom Jericho2 programming guide. ## Full article daily.dev links to this article rather than hosting it. Read it at the original source: ## Questions this post answers ### Is dynamic MAC learning done in hardware or does it require CPU involvement in modern switches? It depends on the ASIC and configuration. Many modern ASICs can update MAC hash tables autonomously in hardware, but hash collision handling is complex enough that implementations often offload it to a CPU — either one embedded in the ASIC or the main NOS CPU. Broadcom ASICs offer configurable modes including 'CPU managed learning'. In chassis or multi-ASIC switches, the NOS CPU is always involved to propagate entries across all ASICs. _Network engineers evaluating switching architectures track these ASIC-level tradeoffs on daily.dev._ ### Why would a switch punt MAC learning to the CPU instead of handling it entirely in the ASIC? Two main reasons: hash collisions and security policy. As the MAC table fills, collision resolution algorithms like cuckoo hashing become too complex for efficient hardware implementation, so many ASICs hand off to a CPU. Additionally, some deployments — particularly at the access/edge — require software to vet every new MAC-to-port entry before updating the forwarding table, to prevent DoS or security issues. _Developers and engineers building or evaluating switching platforms find discussions like this on daily.dev._ ## Similar posts on daily.dev - [Designing an Ethernet Switch ASIC](https://daily.dev/posts/designing-an-ethernet-switch-asic-rmi8a0xuo) · Hacker News · 0 upvotes · 0 comments - [Back to the Metal: AI’s Networking Shift](https://daily.dev/posts/back-to-the-metal-ai-s-networking-shift-jeye2krkn) · The New Stack · 1 upvotes · 0 comments - [Converged north-south networks: the critical path for AI success](https://daily.dev/posts/converged-north-south-networks-the-critical-path-for-ai-success-heod2pxf8) · Cisco · 0 upvotes · 0 comments --- Tags: [#fpga](https://daily.dev/tags/fpga) [View this post on daily.dev](https://daily.dev/posts/dynamic-mac-learning-hardware-or-cpu-activity-ipspace-net-blog-bzdxn9vzw) ```json {"@context":"https://schema.org","@graph":[{"@type":"Organization","@id":"https://daily.dev/#organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180},"sameAs":["https://twitter.com/dailydotdev","https://github.com/dailydotdev","https://www.linkedin.com/company/daily-dev-ltd"]},{"@type":"WebSite","@id":"https://daily.dev/#website","url":"https://daily.dev","name":"daily.dev","publisher":{"@id":"https://daily.dev/#organization"},"potentialAction":{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https://daily.dev/search?q={search_term_string}"},"query-input":"required name=search_term_string"}}]} {"@context":"https://schema.org","@type":"TechArticle","headline":"Dynamic MAC Learning: Hardware or CPU Activity? « ipSpace.net blog","url":"https://daily.dev/posts/dynamic-mac-learning-hardware-or-cpu-activity-ipspace-net-blog-bzdxn9vzw","mainEntityOfPage":{"@type":"WebPage","@id":"https://daily.dev/posts/dynamic-mac-learning-hardware-or-cpu-activity-ipspace-net-blog-bzdxn9vzw"},"datePublished":"2026-08-11T08:54:53.498Z","dateModified":"2026-08-11T09:16:45.351Z","description":"Dynamic MAC learning in hardware switches is more nuanced than commonly assumed. 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Many modern ASICs can update MAC hash tables autonomously in hardware, but hash collision handling is complex enough that implementations often offload it to a CPU — either one embedded in the ASIC or the main NOS CPU. Broadcom ASICs offer configurable modes including 'CPU managed learning'. In chassis or multi-ASIC switches, the NOS CPU is always involved to propagate entries across all ASICs. Network engineers evaluating switching architectures track these ASIC-level tradeoffs on daily.dev."}},{"@type":"Question","name":"Why would a switch punt MAC learning to the CPU instead of handling it entirely in the ASIC?","acceptedAnswer":{"@type":"Answer","text":"Two main reasons: hash collisions and security policy. As the MAC table fills, collision resolution algorithms like cuckoo hashing become too complex for efficient hardware implementation, so many ASICs hand off to a CPU. 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