--- title: fearless_simd v0.6 brings AVX-512 and ways to disable it description: fearless_simd v0.6 adds full AVX-512 support across all operations, including safe invocation via the kernel! macro. AVX-512 is enabled only on Intel Ice Lake... canonical: https://daily.dev/posts/fearless-simd-v0-6-brings-avx-512-and-ways-to-disable-it-wjwtpunwa twitter:card: summary_large_image twitter:site: @dailydotdev og:type: website og:site_name: daily.dev og:title: fearless_simd v0.6 brings AVX-512 and ways to disable it | daily.dev og:description: fearless_simd v0.6 adds full AVX-512 support across all operations, including safe invocation via the kernel! macro. AVX-512 is enabled only on Intel Ice Lake... og:url: https://daily.dev/posts/fearless-simd-v0-6-brings-avx-512-and-ways-to-disable-it-wjwtpunwa og:image: https://api.daily.dev/og/posts/WJwtpUnWa.png og:image:alt: fearless_simd v0.6 brings AVX-512 and ways to disable it og:image:width: 1200 og:image:height: 630 og:locale: en --- > ## Documentation Index > Fetch the complete documentation index at: https://daily.dev/llms.txt > Use this file to discover all available pages before exploring further. # fearless_simd v0.6 brings AVX-512 and ways to disable it **[Linebender](https://daily.dev/sources/linebender)** · 5 min read · 0 upvotes · 0 comments ## Summary fearless_simd v0.6 adds full AVX-512 support across all operations, including safe invocation via the kernel! macro. AVX-512 is enabled only on Intel Ice Lake and later (to avoid Skylake's downclocking issue) and is unrestricted on AMD, since its real benefit comes from extra instructions and doubled registers rather than wider 512-bit vectors. Benchmarks in Vello CPU show a 15% end-to-end runtime improvement over AVX2 even on a Zen 4 CPU without native 512-bit vectors, and with no code changes required. The release also introduces cfg-flag based controls (e.g. disable_dispatch_avx512) to disable specific instruction sets per-function or binary-wide, chosen over Cargo features because the decision belongs to whoever builds the final binary rather than library authors. ## Full article daily.dev links to this article rather than hosting it. Read it at the original source: ## Questions this post answers ### Does fearless_simd v0.6 support AVX-512 in Rust? Yes, fearless_simd v0.6 adds AVX-512 support for all operations, including safely invoking AVX-512 intrinsics through the kernel! macro. AVX-512 is only enabled on Intel CPUs starting with Ice Lake, since earlier Skylake chips downclocked all cores upon hitting an AVX-512 instruction; AMD chips are unaffected and always eligible. _Rust developers tracking SIMD crate updates like fearless_simd's AVX-512 rollout can follow it on daily.dev._ ### How do I disable AVX-512 or other SIMD instruction sets when building a Rust binary with fearless_simd? Set a cfg flag such as RUSTFLAGS=--cfg=disable_dispatch_avx512 for a one-off build, or add it to .cargo/config.toml for all builds. fearless_simd uses cfg flags rather than Cargo features because the choice of instruction sets belongs to whoever compiles the final binary, and cfg flags apply across the whole dependency tree, unlike Cargo features. _Developers tuning binary size and CPU compatibility can track SIMD tooling changes like this on daily.dev._ ### Why do Cargo features not work well for controlling SIMD instruction set selection in a Rust crate? Cargo features are a library-level switch, so the decision on which instruction sets to compile ends up controlled by library authors rather than whoever builds the final binary. Also, if any dependency in the tree enables a feature, it cannot be removed without forking and patching that dependency, which is why fearless_simd instead uses cfg flags that apply across the entire dependency tree. _Rust developers weighing configuration strategies for performance crates can follow such design decisions on daily.dev._ ## Similar posts on daily.dev - [fearless\_simd v0.7: 64-bit integers, improved generics, SSE2, and upcoming v1.0](https://daily.dev/posts/fearless-simd-v0-7-64-bit-integers-improved-generics-sse2-and-upcoming-v1-0-aors3lfex) · Lobsters · 0 upvotes · 0 comments - [SIMD programming in pure Rust](https://daily.dev/posts/simd-programming-in-pure-rust-idnkdlsse) · Hacker News · 2 upvotes · 0 comments --- Tags: [#performance](https://daily.dev/tags/performance), [#rust](https://daily.dev/tags/rust) [View this post on daily.dev](https://daily.dev/posts/fearless-simd-v0-6-brings-avx-512-and-ways-to-disable-it-wjwtpunwa) ```json {"@context":"https://schema.org","@graph":[{"@type":"Organization","@id":"https://daily.dev/#organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180},"sameAs":["https://twitter.com/dailydotdev","https://github.com/dailydotdev","https://www.linkedin.com/company/daily-dev-ltd"]},{"@type":"WebSite","@id":"https://daily.dev/#website","url":"https://daily.dev","name":"daily.dev","publisher":{"@id":"https://daily.dev/#organization"},"potentialAction":{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https://daily.dev/search?q={search_term_string}"},"query-input":"required name=search_term_string"}}]} {"@context":"https://schema.org","@type":"TechArticle","headline":"fearless_simd v0.6 brings AVX-512 and ways to disable it","url":"https://daily.dev/posts/fearless-simd-v0-6-brings-avx-512-and-ways-to-disable-it-wjwtpunwa","mainEntityOfPage":{"@type":"WebPage","@id":"https://daily.dev/posts/fearless-simd-v0-6-brings-avx-512-and-ways-to-disable-it-wjwtpunwa"},"datePublished":"2026-08-31T05:54:34.777Z","dateModified":"2026-08-31T05:54:57.705Z","description":"fearless_simd v0.6 adds full AVX-512 support across all operations, including safe invocation via the kernel! macro. AVX-512 is enabled only on Intel Ice Lake...","image":"https://media.daily.dev/image/upload/s--2-1xRawN--/f_auto/v1722860399/public/Placeholder%2011","thumbnailUrl":"https://media.daily.dev/image/upload/s--2-1xRawN--/f_auto/v1722860399/public/Placeholder%2011","isAccessibleForFree":true,"articleSection":"Linebender","inLanguage":"en","publisher":{"@type":"Organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180}},"author":{"@type":"Organization","name":"Linebender","logo":"https://media.daily.dev/image/upload/logos/placeholder.jpg","url":"https://daily.dev/sources/linebender"},"commentCount":0,"discussionUrl":"https://daily.dev/posts/fearless-simd-v0-6-brings-avx-512-and-ways-to-disable-it-wjwtpunwa","interactionStatistic":[{"@type":"InteractionCounter","interactionType":{"@type":"LikeAction"},"userInteractionCount":0},{"@type":"InteractionCounter","interactionType":{"@type":"CommentAction"},"userInteractionCount":0}],"keywords":"performance,rust","timeRequired":"PT5M"} {"@context":"https://schema.org","@type":"BreadcrumbList","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https://daily.dev"},{"@type":"ListItem","position":2,"name":"Linebender","item":"https://daily.dev/sources/linebender"},{"@type":"ListItem","position":3,"name":"fearless_simd v0.6 brings AVX-512 and ways to disable it"}]} {"@context":"https://schema.org","@type":"FAQPage","@id":"https://daily.dev/posts/fearless-simd-v0-6-brings-avx-512-and-ways-to-disable-it-wjwtpunwa#faq","mainEntity":[{"@type":"Question","name":"Does fearless_simd v0.6 support AVX-512 in Rust?","acceptedAnswer":{"@type":"Answer","text":"Yes, fearless_simd v0.6 adds AVX-512 support for all operations, including safely invoking AVX-512 intrinsics through the kernel! macro. AVX-512 is only enabled on Intel CPUs starting with Ice Lake, since earlier Skylake chips downclocked all cores upon hitting an AVX-512 instruction; AMD chips are unaffected and always eligible. Rust developers tracking SIMD crate updates like fearless_simd's AVX-512 rollout can follow it on daily.dev."}},{"@type":"Question","name":"How do I disable AVX-512 or other SIMD instruction sets when building a Rust binary with fearless_simd?","acceptedAnswer":{"@type":"Answer","text":"Set a cfg flag such as RUSTFLAGS=--cfg=disable_dispatch_avx512 for a one-off build, or add it to .cargo/config.toml for all builds. fearless_simd uses cfg flags rather than Cargo features because the choice of instruction sets belongs to whoever compiles the final binary, and cfg flags apply across the whole dependency tree, unlike Cargo features. Developers tuning binary size and CPU compatibility can track SIMD tooling changes like this on daily.dev."}},{"@type":"Question","name":"Why do Cargo features not work well for controlling SIMD instruction set selection in a Rust crate?","acceptedAnswer":{"@type":"Answer","text":"Cargo features are a library-level switch, so the decision on which instruction sets to compile ends up controlled by library authors rather than whoever builds the final binary. Also, if any dependency in the tree enables a feature, it cannot be removed without forking and patching that dependency, which is why fearless_simd instead uses cfg flags that apply across the entire dependency tree. Rust developers weighing configuration strategies for performance crates can follow such design decisions on daily.dev."}}]} ```