--- title: GCC 17 Now Supports Using -mtune=native -mcpu=native On... description: GCC has merged patches enabling proper support for -mcpu=native and -mtune=native flags on RISC-V systems, allowing the compiler to automatically detect and... canonical: https://daily.dev/posts/gcc-17-now-supports-using--mtune-native--mcpu-native-on-risc-v-djbpasrzx twitter:card: summary_large_image twitter:site: @dailydotdev og:type: website og:site_name: daily.dev og:title: GCC 17 Now Supports Using -mtune=native -mcpu=native On RISC-V | daily.dev og:description: GCC has merged patches enabling proper support for -mcpu=native and -mtune=native flags on RISC-V systems, allowing the compiler to automatically detect and... og:url: https://daily.dev/posts/gcc-17-now-supports-using--mtune-native--mcpu-native-on-risc-v-djbpasrzx og:image: https://api.daily.dev/og/posts/DJbPASrzX.png og:image:alt: GCC 17 Now Supports Using -mtune=native -mcpu=native On RISC-V og:image:width: 1200 og:image:height: 630 og:locale: en --- > ## Documentation Index > Fetch the complete documentation index at: https://daily.dev/llms.txt > Use this file to discover all available pages before exploring further. # GCC 17 Now Supports Using -mtune=native -mcpu=native On RISC-V **[Phoronix](https://daily.dev/sources/phoronix)** · 1 min read · 0 upvotes · 0 comments ## Summary GCC has merged patches enabling proper support for -mcpu=native and -mtune=native flags on RISC-V systems, allowing the compiler to automatically detect and tune code generation for the host CPU instead of requiring manual specification like 'sifive-p550' or 'spacemit-x100'. The patch, authored by SiFive's Kito Cheng, is slated for the GCC 17.1 release expected in early 2027. A current limitation remains for multi-core-type RISC-V designs like the SpacemiT X100, where GCC picks the CPU type based on whichever core the compiler process happens to run on. ## Full article daily.dev links to this article rather than hosting it. Read it at the original source: ## Questions this post answers ### Does GCC support -mcpu=native and -mtune=native on RISC-V? Yes, as of a patch merged into GCC Git by SiFive's Kito Cheng, GCC correctly handles the -mcpu=native and -mtune=native flags on RISC-V, automatically detecting the host CPU instead of requiring developers to manually specify values like sifive-p550 or spacemit-x100. This support is slated for the GCC 17.1 release, expected in early 2027. _Compiler engineers tracking GCC RISC-V tuning changes can follow release updates like this on daily.dev._ ### How does GCC handle native CPU detection on RISC-V chips with multiple core types like the SpacemiT X100? GCC picks the CPU type based on whichever core the compiler process happens to be running on when using -mcpu=native, which is a known current limitation for asymmetric multi-core RISC-V designs such as the SpacemiT A100 and X100 combinations that mix different core types on one chip. _Developers building for heterogeneous RISC-V hardware can keep tabs on toolchain fixes like this via daily.dev._ ## Similar posts on daily.dev - [GCC Patches Added -mcpu=native -mtune=native Support For RISC-V](https://daily.dev/posts/gcc-patches-added--mcpu-native--mtune-native-support-for-risc-v-7bldbxf6r) · Phoronix · 0 upvotes · 0 comments - [GCC 17 Compiler Lands SpacemiT X100 Core Targeting](https://daily.dev/posts/gcc-17-compiler-lands-spacemit-x100-core-targeting-21vwfvqan) · Phoronix · 0 upvotes · 0 comments - [Hygon C86-4G CPU Support Added To The GCC 17 Compiler](https://daily.dev/posts/hygon-c86-4g-cpu-support-added-to-the-gcc-17-compiler-wkn6rpfvp) · Phoronix · 0 upvotes · 0 comments - [GCC 17 Compiler Adding "-m128bit-atomic" For 128-bit Atomic Memory Operations](https://daily.dev/posts/gcc-17-compiler-adding--m128bit-atomic-for-128-bit-atomic-memory-operations-rkuku3p4z) · Phoronix · 1 upvotes · 0 comments - [GCC 17 Compiler Merges Initial Support For Intel/AMD AI Compute Extensions "ACE"](https://daily.dev/posts/gcc-17-compiler-merges-initial-support-for-intel-amd-ai-compute-extensions-ace--zwwfphik0) · Phoronix · 0 upvotes · 0 comments --- Tags: [#linux](https://daily.dev/tags/linux) [View this post on daily.dev](https://daily.dev/posts/gcc-17-now-supports-using--mtune-native--mcpu-native-on-risc-v-djbpasrzx) ```json {"@context":"https://schema.org","@graph":[{"@type":"Organization","@id":"https://daily.dev/#organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180},"sameAs":["https://twitter.com/dailydotdev","https://github.com/dailydotdev","https://www.linkedin.com/company/daily-dev-ltd"]},{"@type":"WebSite","@id":"https://daily.dev/#website","url":"https://daily.dev","name":"daily.dev","publisher":{"@id":"https://daily.dev/#organization"},"potentialAction":{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https://daily.dev/search?q={search_term_string}"},"query-input":"required name=search_term_string"}}]} {"@context":"https://schema.org","@type":"TechArticle","headline":"GCC 17 Now Supports Using -mtune=native -mcpu=native On RISC-V","url":"https://daily.dev/posts/gcc-17-now-supports-using--mtune-native--mcpu-native-on-risc-v-djbpasrzx","mainEntityOfPage":{"@type":"WebPage","@id":"https://daily.dev/posts/gcc-17-now-supports-using--mtune-native--mcpu-native-on-risc-v-djbpasrzx"},"datePublished":"2026-09-03T10:25:33.410Z","dateModified":"2026-09-03T10:51:55.574Z","description":"GCC has merged patches enabling proper support for -mcpu=native and -mtune=native flags on RISC-V systems, allowing the compiler to automatically detect and...","image":"https://media.daily.dev/image/upload/f_auto,q_auto/v1/posts/ce60e7a59bc64974874f5e473c7a5ed1?_a=AQAEuop","thumbnailUrl":"https://media.daily.dev/image/upload/f_auto,q_auto/v1/posts/ce60e7a59bc64974874f5e473c7a5ed1?_a=AQAEuop","isAccessibleForFree":true,"articleSection":"Phoronix","inLanguage":"en","publisher":{"@type":"Organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180}},"author":{"@type":"Organization","name":"Phoronix","logo":"https://media.daily.dev/image/upload/t_logo,f_auto/v1/logos/6a26ba379dd64932830aa0c9803dd7ee","url":"https://daily.dev/sources/phoronix"},"commentCount":0,"discussionUrl":"https://daily.dev/posts/gcc-17-now-supports-using--mtune-native--mcpu-native-on-risc-v-djbpasrzx","interactionStatistic":[{"@type":"InteractionCounter","interactionType":{"@type":"LikeAction"},"userInteractionCount":0},{"@type":"InteractionCounter","interactionType":{"@type":"CommentAction"},"userInteractionCount":0}],"keywords":"linux","timeRequired":"PT1M"} {"@context":"https://schema.org","@type":"BreadcrumbList","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https://daily.dev"},{"@type":"ListItem","position":2,"name":"Phoronix","item":"https://daily.dev/sources/phoronix"},{"@type":"ListItem","position":3,"name":"GCC 17 Now Supports Using -mtune=native -mcpu=native On RISC-V"}]} {"@context":"https://schema.org","@type":"FAQPage","@id":"https://daily.dev/posts/gcc-17-now-supports-using--mtune-native--mcpu-native-on-risc-v-djbpasrzx#faq","mainEntity":[{"@type":"Question","name":"Does GCC support -mcpu=native and -mtune=native on RISC-V?","acceptedAnswer":{"@type":"Answer","text":"Yes, as of a patch merged into GCC Git by SiFive's Kito Cheng, GCC correctly handles the -mcpu=native and -mtune=native flags on RISC-V, automatically detecting the host CPU instead of requiring developers to manually specify values like sifive-p550 or spacemit-x100. This support is slated for the GCC 17.1 release, expected in early 2027. Compiler engineers tracking GCC RISC-V tuning changes can follow release updates like this on daily.dev."}},{"@type":"Question","name":"How does GCC handle native CPU detection on RISC-V chips with multiple core types like the SpacemiT X100?","acceptedAnswer":{"@type":"Answer","text":"GCC picks the CPU type based on whichever core the compiler process happens to be running on when using -mcpu=native, which is a known current limitation for asymmetric multi-core RISC-V designs such as the SpacemiT A100 and X100 combinations that mix different core types on one chip. Developers building for heterogeneous RISC-V hardware can keep tabs on toolchain fixes like this via daily.dev."}}]} ```