A comprehensive tour of how CPU caches work, using an office analogy to explain the full hierarchy from L1 to RAM. Covers cache lines, set-associative structure (sets, ways, tags), replacement policies (LRU, pseudo-LRU, NRU), write strategies (write-through vs write-back, write-allocate vs no-write-allocate), inclusive vs exclusive cache hierarchies, and the hardware difference between SRAM and DRAM. Also explains data-oriented vs object-oriented memory layout and how spatial/temporal locality affect cache performance.
Table of contents
What we’ll cover1. Cache overview2. Data layout and cache friendliness3. Locality of reference4. Cache lines5. Sets, ways, and tags6. Replacement policies7. Cache writes and consistency8. Write-through vs write-back9. Write-allocate vs no-write-allocate10. Cache hierarchy: L1, L2, L311. SRAM vs DRAM12. Summary3 Impressions