--- title: How The Intel 8087 FPU Knows Which Instructions To Execute description: A deep dive into how the Intel 8087 FPU co-processor identifies and executes its instructions when sharing a bus with the 8086/8088 CPU. The mechanism relies... canonical: https://daily.dev/posts/how-the-intel-8087-fpu-knows-which-instructions-to-execute-xq7uk4umr twitter:card: summary_large_image twitter:site: @dailydotdev og:type: website og:site_name: daily.dev og:title: How The Intel 8087 FPU Knows Which Instructions To Execute | daily.dev og:description: A deep dive into how the Intel 8087 FPU co-processor identifies and executes its instructions when sharing a bus with the 8086/8088 CPU. The mechanism relies... og:url: https://daily.dev/posts/how-the-intel-8087-fpu-knows-which-instructions-to-execute-xq7uk4umr og:image: https://api.daily.dev/og/posts/XQ7uk4UMr.png og:image:alt: How The Intel 8087 FPU Knows Which Instructions To Execute og:image:width: 1200 og:image:height: 630 og:locale: en --- > ## Documentation Index > Fetch the complete documentation index at: https://daily.dev/llms.txt > Use this file to discover all available pages before exploring further. # How The Intel 8087 FPU Knows Which Instructions To Execute **[Hackaday](https://daily.dev/sources/hackaday)** · 2 min read · 0 upvotes · 0 comments ## Summary A deep dive into how the Intel 8087 FPU co-processor identifies and executes its instructions when sharing a bus with the 8086/8088 CPU. The mechanism relies on eight special ESCAPE opcodes reserved for the co-processor, with data sharing occurring through system memory via a BIU register. Instruction decoding is handled primarily by a microcode engine backed by a compact ROM with only 22 entry points, supplemented by logic gates and PLAs to keep silicon area manageable. The article highlights the clever engineering trade-offs made to implement complex floating-point operations like cosine within severe hardware constraints of the era. ## Full article daily.dev links to this article rather than hosting it. Read it at the original source: ## Similar posts on daily.dev - [The Intel 8087 And Conditional Microcode Tests](https://daily.dev/posts/the-intel-8087-and-conditional-microcode-tests-asdopknlo) · Hackaday · 0 upvotes · 0 comments - [Conditions in the Intel 8087 floating-point chip's microcode](https://daily.dev/posts/conditions-in-the-intel-8087-floating-point-chip-s-microcode-pfftxg6y6) · Hacker News · 1 upvotes · 0 comments - [The stack circuitry of the Intel 8087 floating point chip, reverse-engineered](https://daily.dev/posts/the-stack-circuitry-of-the-intel-8087-floating-point-chip-reverse-engineered-damxz0ovc) · Hacker News · 0 upvotes · 0 comments - [The Inner Workings Of The Intel 8086’s Arithmetic Logic Unit](https://daily.dev/posts/the-inner-workings-of-the-intel-8086-s-arithmetic-logic-unit-xnfeogipn) · Hackaday · 1 upvotes · 0 comments - [Notes on the Intel 8086 processor's arithmetic-logic unit](https://daily.dev/posts/notes-on-the-intel-8086-processor-s-arithmetic-logic-unit-d8w6bkxpq) · Hacker News · 0 upvotes · 0 comments --- Tags: [#hardware](https://daily.dev/tags/hardware), [#intel](https://daily.dev/tags/intel), [#retrocomputing](https://daily.dev/tags/retrocomputing), [#reverse-engineering](https://daily.dev/tags/reverse-engineering) [View this post on daily.dev](https://daily.dev/posts/how-the-intel-8087-fpu-knows-which-instructions-to-execute-xq7uk4umr) ```json {"@context":"https://schema.org","@graph":[{"@type":"Organization","@id":"https://daily.dev/#organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180},"sameAs":["https://twitter.com/dailydotdev","https://github.com/dailydotdev","https://www.linkedin.com/company/daily-dev-ltd"]},{"@type":"WebSite","@id":"https://daily.dev/#website","url":"https://daily.dev","name":"daily.dev","publisher":{"@id":"https://daily.dev/#organization"},"potentialAction":{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https://daily.dev/search?q={search_term_string}"},"query-input":"required name=search_term_string"}}]} {"@context":"https://schema.org","@type":"TechArticle","headline":"How The Intel 8087 FPU Knows Which Instructions To Execute","url":"https://daily.dev/posts/how-the-intel-8087-fpu-knows-which-instructions-to-execute-xq7uk4umr","mainEntityOfPage":{"@type":"WebPage","@id":"https://daily.dev/posts/how-the-intel-8087-fpu-knows-which-instructions-to-execute-xq7uk4umr"},"datePublished":"2026-02-22T00:16:45.896Z","dateModified":"2026-03-15T03:33:22.932Z","description":"A deep dive into how the Intel 8087 FPU co-processor identifies and executes its instructions when sharing a bus with the 8086/8088 CPU. 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