Imec has released its updated semiconductor technology roadmap at its annual ITF forum, projecting that complementary FETs (CFETs) will enter commercial production around 2033. CFETs stack PMOS and NMOS transistors vertically instead of side by side, potentially halving circuit area. Intel, Samsung, and TSMC are all building CFET prototypes, though the optimal manufacturing approach remains unsettled. Key challenges include electrically isolating the stacked transistors and addressing PMOS/NMOS speed mismatches. Looking further ahead, Imec anticipates a shift to 2D semiconductors (like molybdenum disulfide) around 2041, primarily for power efficiency gains. The roadmap also covers advances in 3D chip packaging, hybrid bonding at 200nm pitch, and a concept called CMOS 2.0 where chips are built from fused layers each optimized for specific functions.
