--- title: Intel Starts Shipping High-NA EUV Silicon | daily.dev description: Intel has begun shipping Panther Lake (Core Ultra Series 3) notebook processors with layers patterned using ASML's High-NA EUV scanner at its D1X fab in Oregon... canonical: https://daily.dev/posts/intel-starts-shipping-high-na-euv-silicon-ykjhcatbt twitter:card: summary_large_image twitter:site: @dailydotdev og:type: website og:site_name: daily.dev og:title: Intel Starts Shipping High-NA EUV Silicon | daily.dev og:description: Intel has begun shipping Panther Lake (Core Ultra Series 3) notebook processors with layers patterned using ASML's High-NA EUV scanner at its D1X fab in Oregon... og:url: https://daily.dev/posts/intel-starts-shipping-high-na-euv-silicon-ykjhcatbt og:image: https://api.daily.dev/og/posts/YkJhcatBT.png og:image:alt: Intel Starts Shipping High-NA EUV Silicon og:image:width: 1200 og:image:height: 630 og:locale: en --- > ## Documentation Index > Fetch the complete documentation index at: https://daily.dev/llms.txt > Use this file to discover all available pages before exploring further. # Intel Starts Shipping High-NA EUV Silicon **[Hacker News](https://daily.dev/sources/hn)** · 8 min read · 1 upvotes · 0 comments ## Summary Intel has begun shipping Panther Lake (Core Ultra Series 3) notebook processors with layers patterned using ASML's High-NA EUV scanner at its D1X fab in Oregon — marking the first time High-NA EUV has entered high-volume manufacturing. The High-NA tool (0.55 NA vs. the standard 0.33 NA) can print finer features in a single exposure that would otherwise require two or three Low-NA passes, but comes at roughly $380M per unit and 2.5x the per-exposure cost. Intel dual-qualified the High-NA layers alongside Low-NA on 18A to de-risk the transition, building process expertise ahead of 14A/10A nodes where High-NA becomes more critical. TSMC has been more conservative, skipping High-NA for its 2nm and A16 nodes. ASML is ramping production to ~20 systems/year by 2028, with SK Hynix, Samsung, and IBM also adopting the technology. The matched yield result on Panther Lake is cited as strong evidence the tool is production-ready. ## Full article daily.dev links to this article rather than hosting it. Read it at the original source: ## Questions this post answers ### Has Intel started using High-NA EUV lithography in actual production chips? Yes, as of July 15, 2026, ASML confirmed Intel Foundry has taken High-NA EUV into high-volume manufacturing, patterning a subset of layers on Panther Lake notebook processors (Core Ultra Series 3) built on Intel 18A. These layers are dual-qualified on both Low-NA and High-NA tools, and Intel reports yields matching mature Low-NA EUV scanners. _Track how High-NA EUV adoption reshapes chip roadmaps and sourcing decisions on daily.dev._ ### How much does a High-NA EUV scanner cost compared to a standard EUV machine? A High-NA EUV system costs close to $380 million, roughly two to three times the price of a standard Low-NA EUV scanner. Installing one requires around 250 crates and several months of on-site work. Despite the cost, ASML had ten to twenty orders booked by early 2024 from customers including Intel, SK hynix, Samsung, and a New York state facility leased to IBM. _Developers weighing fab economics can follow EUV cost trends and tooling shifts on daily.dev._ ### When does High-NA EUV lithography become cheaper than Low-NA multi-patterning? SemiAnalysis modeling, based on IBM's 2025 conference research, put the cost crossover around 2030 for most chip layers, since a single High-NA exposure costs about two and a half times a Low-NA exposure. Low-NA double-patterning stays cheaper until a pattern requires three or more masks, which is why TSMC has skipped High-NA for its 2nm and A16 nodes. _Keep up with lithography cost curves shaping future process nodes via daily.dev._ ## Similar posts on daily.dev - [ASML’s $400M chipmaking machine just shipped its first laptop processors](https://daily.dev/posts/asml-s-400m-chipmaking-machine-just-shipped-its-first-laptop-processors-qeq8bvp7b) · The Next Web · 0 upvotes · 0 comments - [TSMC backs ASML’s plan for bigger masks so its newest machines can print AI’s biggest chips](https://daily.dev/posts/tsmc-backs-asml-s-plan-for-bigger-masks-so-its-newest-machines-can-print-ai-s-biggest-chips-dnvbfelxk) · The Next Web · 0 upvotes · 0 comments - [The world’s most complex machine](https://daily.dev/posts/the-world-s-most-complex-machine-f6llcj1pv) · Hacker News · 0 upvotes · 0 comments - [ASML sets its sights on the next era of AI silicon](https://daily.dev/posts/asml-sets-its-sights-on-the-next-era-of-ai-silicon-ihfzlolmn) · TechCentral · 0 upvotes · 0 comments --- Tags: [#intel](https://daily.dev/tags/intel) [View this post on daily.dev](https://daily.dev/posts/intel-starts-shipping-high-na-euv-silicon-ykjhcatbt) ```json {"@context":"https://schema.org","@graph":[{"@type":"Organization","@id":"https://daily.dev/#organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180},"sameAs":["https://twitter.com/dailydotdev","https://github.com/dailydotdev","https://www.linkedin.com/company/daily-dev-ltd"]},{"@type":"WebSite","@id":"https://daily.dev/#website","url":"https://daily.dev","name":"daily.dev","publisher":{"@id":"https://daily.dev/#organization"},"potentialAction":{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https://daily.dev/search?q={search_term_string}"},"query-input":"required name=search_term_string"}}]} {"@context":"https://schema.org","@type":"TechArticle","headline":"Intel Starts Shipping High-NA EUV Silicon","url":"https://daily.dev/posts/intel-starts-shipping-high-na-euv-silicon-ykjhcatbt","mainEntityOfPage":{"@type":"WebPage","@id":"https://daily.dev/posts/intel-starts-shipping-high-na-euv-silicon-ykjhcatbt"},"datePublished":"2026-07-22T09:29:34.371Z","dateModified":"2026-09-14T06:01:36.056Z","description":"Intel has begun shipping Panther Lake (Core Ultra Series 3) notebook processors with layers patterned using ASML's High-NA EUV scanner at its D1X fab in Oregon...","image":"https://media.daily.dev/image/upload/f_auto,q_auto/v1/posts/10baef8f6c7af3e196b7ac0793e2a7e4?_a=AQAEuop","thumbnailUrl":"https://media.daily.dev/image/upload/f_auto,q_auto/v1/posts/10baef8f6c7af3e196b7ac0793e2a7e4?_a=AQAEuop","isAccessibleForFree":true,"articleSection":"Hacker News","inLanguage":"en","publisher":{"@type":"Organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180}},"author":{"@type":"Organization","name":"Hacker News","logo":"https://media.daily.dev/image/upload/t_logo,f_auto/v1/logos/hn","url":"https://daily.dev/sources/hn"},"commentCount":0,"discussionUrl":"https://daily.dev/posts/intel-starts-shipping-high-na-euv-silicon-ykjhcatbt","interactionStatistic":[{"@type":"InteractionCounter","interactionType":{"@type":"LikeAction"},"userInteractionCount":1},{"@type":"InteractionCounter","interactionType":{"@type":"CommentAction"},"userInteractionCount":0}],"keywords":"intel","timeRequired":"PT8M"} {"@context":"https://schema.org","@type":"BreadcrumbList","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https://daily.dev"},{"@type":"ListItem","position":2,"name":"Hacker News","item":"https://daily.dev/sources/hn"},{"@type":"ListItem","position":3,"name":"Intel Starts Shipping High-NA EUV Silicon"}]} {"@context":"https://schema.org","@type":"FAQPage","@id":"https://daily.dev/posts/intel-starts-shipping-high-na-euv-silicon-ykjhcatbt#faq","mainEntity":[{"@type":"Question","name":"Has Intel started using High-NA EUV lithography in actual production chips?","acceptedAnswer":{"@type":"Answer","text":"Yes, as of July 15, 2026, ASML confirmed Intel Foundry has taken High-NA EUV into high-volume manufacturing, patterning a subset of layers on Panther Lake notebook processors (Core Ultra Series 3) built on Intel 18A. These layers are dual-qualified on both Low-NA and High-NA tools, and Intel reports yields matching mature Low-NA EUV scanners. Track how High-NA EUV adoption reshapes chip roadmaps and sourcing decisions on daily.dev."}},{"@type":"Question","name":"How much does a High-NA EUV scanner cost compared to a standard EUV machine?","acceptedAnswer":{"@type":"Answer","text":"A High-NA EUV system costs close to $380 million, roughly two to three times the price of a standard Low-NA EUV scanner. Installing one requires around 250 crates and several months of on-site work. Despite the cost, ASML had ten to twenty orders booked by early 2024 from customers including Intel, SK hynix, Samsung, and a New York state facility leased to IBM. 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