Part 9 of a microcontroller tutorial series covering how to simulate parallel task execution on a single-core MCU using a single hardware timer. Explains a millisecond-tick ISR approach where each task is assigned a deadline, and a cyclic executive main loop checks those deadlines each iteration. Covers safe deadline comparison using 2s complement signed arithmetic to handle timer rollover, ISR race conditions on 8-bit devices requiring atomic access, and the SysTick timer on STM32. Includes a complete STM32 LCD driver using atomic GPIO BSRR/BRR registers, a timer-based ms_delay(), and a working demo with two counters, an LCD display, and button-driven resets. Also discusses an optimization-level bug where clearing an interrupt flag too late caused double-firing of the ISR.
