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description: A Linux kernel patch fixes a performance regression on the AMD Ryzen AI 9 HX 370 caused by Cache Aware Scheduling. The scheduler was frequently keeping Clang...
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# Linux Fixes AMD Ryzen AI 9 HX 370 Regression Due To Cache Aware Scheduling

**[Phoronix](https://daily.dev/sources/phoronix)** · 3 min read · 0 upvotes · 0 comments

## Summary

A Linux kernel patch fixes a performance regression on the AMD Ryzen AI 9 HX 370 caused by Cache Aware Scheduling. The scheduler was frequently keeping Clang full-LTO compilation tasks on the slower 'little' Zen 5C cores instead of moving them to faster performance cores. The Zen 5C cores run at 3.3GHz versus 5.1GHz and have half the L3 cache, so misplacement hurt builds twice over. The fix, merged via the scheduler fixes pull request, now prioritizes asymmetric packing over LLC balancing for regular and active load balancing and is marked for back-porting to the 7.2 and 7.3 stable kernels.

## Full article

daily.dev links to this article rather than hosting it. Read it at the original source: <https://www.phoronix.com/news/Linux-CAS-Regression-AMD-HX-370>

## Questions this post answers

### Why does Clang full-LTO compilation run slower on my AMD Ryzen AI 9 HX 370 since a recent kernel update?

Cache Aware Scheduling was pinning compilation tasks to the slower Zen 5C 'little' cores, which run at 3.3GHz versus 5.1GHz on the performance cores and have half the L3 cache, roughly 8MB versus 16MB. This double penalty made full-LTO builds much slower than on pre-cache-aware-scheduling kernels. A fix merged into Linux now prioritizes moving tasks to faster idle cores over keeping cache locality.

_Track kernel scheduler fixes like this on daily.dev before they bite your build pipeline._

### What changed in the Linux scheduler to fix the conflict between asym packing and cache aware scheduling?

The scheduler now lets asym packing win when it tries to migrate a task to an idle core with higher priority than its source CPU, instead of keeping the task co-located on the same last-level cache. Asym packing and cache aware scheduling expressed conflicting placement strategies, and the fix prioritizes asym packing over LLC balancing for both regular and active load balancing.

_Developers tuning hybrid-core performance can follow scheduler changes like this one on daily.dev._

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- [Linux's Cache Aware Scheduling On AMD Ryzen 9 9950X3D 3D V-Cache](https://daily.dev/posts/linux-s-cache-aware-scheduling-on-amd-ryzen-9-9950x3d-3d-v-cache-3bdru1tfm) · Phoronix · 0 upvotes · 0 comments
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---

Tags: [#linux](https://daily.dev/tags/linux), [#performance](https://daily.dev/tags/performance), [#hardware](https://daily.dev/tags/hardware)

[View this post on daily.dev](https://daily.dev/posts/linux-fixes-amd-ryzen-ai-9-hx-370-regression-due-to-cache-aware-scheduling-vqefvgznv)

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