NVIDIA's NVLink Fusion technology now incorporates NVHBM, a custom HBM base-die design co-developed with memory vendors that boosts memory bandwidth by up to 30%, frees up to 25% more compute die area, and cuts HBM power by up to 15% compared with standard HBM4e. Combined, these gains yield roughly a 30% end-to-end performance improvement per custom XPU. NVHBM achieves area savings by moving the memory controller into the 3D HBM stack and using a custom PHY, reducing PHY and support area by up to 67% versus the JEDEC HBM4e standard. At data-center scale, the power savings could free headroom for thousands of additional XPUs in a gigawatt-class facility. NVLink Fusion lets hyperscalers and AI-native companies integrate custom XPUs and CPUs into NVIDIA's scale-up/scale-out rack architecture (MGX), reducing integration complexity and time to market for semi-custom AI factories.
Table of contents
Why bandwidth, die area, and power drive accelerator designThe memory bandwidth bottleneck in modern AI acceleratorsMore package area, more flexibilityPower savings for efficient scalingCombining NVLink Fusion with NVHBM at rack scaleThe next phase of custom AI siliconQuestions this post answers
What performance benefits does NVIDIA NVHBM provide compared to standard HBM4e?
NVHBM delivers up to 30% more memory bandwidth per stack, up to 25% more usable compute die area, and up to 15% lower HBM power usage compared with standard HBM4e. Combined, these improvements translate into roughly a 30% overall end-to-end performance increase per custom XPU when paired with NVLink Fusion. Engineers evaluating custom AI accelerator memory options can track chip-level benchmarks like these on daily.dev.
How does NVHBM save die area compared to standard HBM4e?
NVHBM uses a custom base die with a redesigned physical memory interface that moves the memory controller into the 3D HBM stack and integrates a custom PHY, reducing wider standard interface connections. This cuts PHY and support area by up to 67% compared with the JEDEC HBM4e standard and provides up to 80% more usable silicon across the layout, freeing up to 30% more main-die silicon for compute. Teams comparing custom silicon memory architectures can follow developments like this on daily.dev.
What is NVIDIA NVLink Fusion and how does it relate to custom AI chips?
NVLink Fusion is NVIDIA's connective technology and IP that lets hyperscalers and AI-native companies integrate custom XPUs and CPUs into NVIDIA's AI infrastructure platform, using NVIDIA's scale-up and scale-out stack and MGX rack-scale architecture. It now incorporates NVHBM, a custom HBM base-die technology, at the package level to boost bandwidth, area, and power efficiency for these custom chips. Infrastructure teams weighing custom silicon versus off-the-shelf GPUs can follow this space on daily.dev.