--- title: "NVIDIA NVLink Fusion Brings NVHBM to Next-Generation AI Infrastructure" url: https://daily.dev/posts/nvidia-nvlink-fusion-brings-nvhbm-to-next-generation-ai-infrastructure-qxnei0p1w source_url: https://developer.nvidia.com/blog/nvidia-nvlink-fusion-brings-nvhbm-to-next-generation-ai-infrastructure type: article source: "NVIDIA Developer" published: 2026-08-26T21:09:15.069Z updated: 2026-08-27T03:51:39.497Z tags: ["hardware", "nvidia", "ai-infrastructure"] reading_time: 7 upvotes: 0 comments: 0 language: en --- > ## Documentation Index > Fetch the complete documentation index at: https://daily.dev/llms.txt > Use this file to discover all available pages before exploring further. # NVIDIA NVLink Fusion Brings NVHBM to Next-Generation AI Infrastructure **[NVIDIA Developer](https://daily.dev/sources/nvidiadev)** · 7 min read · 0 upvotes · 0 comments ## Summary NVIDIA's NVLink Fusion technology now incorporates NVHBM, a custom HBM base-die design co-developed with memory vendors that boosts memory bandwidth by up to 30%, frees up to 25% more compute die area, and cuts HBM power by up to 15% compared with standard HBM4e. Combined, these gains yield roughly a 30% end-to-end performance improvement per custom XPU. NVHBM achieves area savings by moving the memory controller into the 3D HBM stack and using a custom PHY, reducing PHY and support area by up to 67% versus the JEDEC HBM4e standard. At data-center scale, the power savings could free headroom for thousands of additional XPUs in a gigawatt-class facility. NVLink Fusion lets hyperscalers and AI-native companies integrate custom XPUs and CPUs into NVIDIA's scale-up/scale-out rack architecture (MGX), reducing integration complexity and time to market for semi-custom AI factories. ## Full article daily.dev links to this article rather than hosting it. Read it at the original source: ## Questions this post answers ### What performance benefits does NVIDIA NVHBM provide compared to standard HBM4e? NVHBM delivers up to 30% more memory bandwidth per stack, up to 25% more usable compute die area, and up to 15% lower HBM power usage compared with standard HBM4e. Combined, these improvements translate into roughly a 30% overall end-to-end performance increase per custom XPU when paired with NVLink Fusion. _Engineers evaluating custom AI accelerator memory options can track chip-level benchmarks like these on daily.dev._ ### How does NVHBM save die area compared to standard HBM4e? NVHBM uses a custom base die with a redesigned physical memory interface that moves the memory controller into the 3D HBM stack and integrates a custom PHY, reducing wider standard interface connections. This cuts PHY and support area by up to 67% compared with the JEDEC HBM4e standard and provides up to 80% more usable silicon across the layout, freeing up to 30% more main-die silicon for compute. _Teams comparing custom silicon memory architectures can follow developments like this on daily.dev._ ### What is NVIDIA NVLink Fusion and how does it relate to custom AI chips? NVLink Fusion is NVIDIA's connective technology and IP that lets hyperscalers and AI-native companies integrate custom XPUs and CPUs into NVIDIA's AI infrastructure platform, using NVIDIA's scale-up and scale-out stack and MGX rack-scale architecture. It now incorporates NVHBM, a custom HBM base-die technology, at the package level to boost bandwidth, area, and power efficiency for these custom chips. _Infrastructure teams weighing custom silicon versus off-the-shelf GPUs can follow this space on daily.dev._ ## Similar posts on daily.dev - [NVIDIA NVLink: The Scale-Up Network for AI Factories](https://daily.dev/posts/nvidia-nvlink-the-scale-up-network-for-ai-factories-ebmkgal2a) · NVIDIA Developer · 0 upvotes · 0 comments --- Tags: [#hardware](https://daily.dev/tags/hardware), [#nvidia](https://daily.dev/tags/nvidia), [#ai-infrastructure](https://daily.dev/tags/ai-infrastructure) [View this post on daily.dev](https://daily.dev/posts/nvidia-nvlink-fusion-brings-nvhbm-to-next-generation-ai-infrastructure-qxnei0p1w)