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title: NXP MCX A5 Cortex-M33 MCU family supports 10BASE-T1S...
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# NXP MCX A5 Cortex-M33 MCU family supports 10BASE-T1S Single Pair Ethernet and Post-Quantum Cryptography

**[CNX Software](https://daily.dev/sources/cnx-software)** · 5 min read · 1 upvotes · 0 comments

## Summary

NXP has launched the MCX A5 family of Cortex-M33 microcontrollers featuring an integrated 10BASE-T1S Single Pair Ethernet digital PHY and a 10/100Mbps Ethernet MAC, aimed at industrial and edge networking applications like PLCs, remote I/O, and building/energy management systems. The MCXA577 flagship variant runs up to 240 MHz with up to 2MB dual-bank Flash and 640KB SRAM, plus an EdgeLock security accelerator supporting secure boot with post-quantum cryptography hybrid support, secure firmware updates, and anti-tamper detection, targeting PSA Level 3 and SESIP Level 3 certifications. Four SKUs are listed, with software support planned for MCUXpresso, Zephyr RTOS, and select Rust support. NXP offers the FRDM-MCXA577 development board, though detailed availability info remains limited. The chips are sampling now, with general availability expected in Q4 2026.

## Full article

daily.dev links to this article rather than hosting it. Read it at the original source: <https://www.cnx-software.com/2026/08/19/nxp-mcx-a5-cortex-m33-mcu-family-supports-10base-t1s-single-pair-ethernet-and-post-quantum-cryptography>

## Questions this post answers

### What is the NXP MCX A5 MCU family and what makes its Ethernet support different?

The MCX A5 is a Cortex-M33 microcontroller family from NXP that integrates a 10/100Mbps Ethernet MAC and a 10BASE-T1S Single Pair Ethernet digital PHY directly on-chip, running up to 240 MHz with up to 2MB flash and 640KB SRAM. Normally 10BASE-T1S requires an external PMD transceiver such as NXP's TJF1410 or Microchip's LAN867x/LAN865x plus a separate host MCU, but the MCX A5 combines these into a single chip.

_Teams evaluating single-pair Ethernet options for industrial edge nodes can track MCU comparisons like this on daily.dev._

### Does the NXP MCX A5 MCU support post-quantum cryptography?

Yes, the MCX A5 family includes secure boot with post-quantum cryptography hybrid support, backed by an EdgeLock security accelerator featuring a TRNG, public key cryptography engine (ECC, RSA), and a security and general-purpose interface (SGI) supporting AES256, SHA-2, PQC, and a hardware KeyStore. The chip targets PSA Level 3 and SESIP Level 3 security certifications.

_Developers planning PQC-ready secure boot for industrial MCUs can follow announcements like this on daily.dev._

### When will the NXP FRDM-MCXA577 development board be available and what does it support?

The FRDM-MCXA577 board, based on the MCXA577 MCU, was not yet available at time of writing, though the MCX A5 family itself is sampling now with general availability expected in Q4 2026. The board includes an onboard MCU-Link Lite debugger and Arduino, mikroBUS, and Pmod expansion headers, with documentation listing support for FreeRTOS, MCUboot, FatFs, FreeMASTER, and Trusted Firmware-M, plus in-progress Zephyr support.

_Engineers waiting on dev board availability for a new MCU can track release timing updates on daily.dev._

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---

Tags: [#quantum-computing](https://daily.dev/tags/quantum-computing), [#embedded](https://daily.dev/tags/embedded)

[View this post on daily.dev](https://daily.dev/posts/nxp-mcx-a5-cortex-m33-mcu-family-supports-10base-t1s-single-pair-ethernet-and-post-quantum-cryptogra-ebkqtbmjg)

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