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title: Performance impact of Alignment | daily.dev
description: Memory alignment significantly affects SIMD vectorization performance, both for auto-vectorization and Java's Vector API. Benchmarks on x64 AVX512 and Aarch64...
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# Performance impact of Alignment

**[Awesome Java Newsletter](https://daily.dev/sources/java_libhunt)** · 15 min read · 1 upvotes · 0 comments

## Summary

Memory alignment significantly affects SIMD vectorization performance, both for auto-vectorization and Java's Vector API. Benchmarks on x64 AVX512 and Aarch64 NEON machines show that misaligned loads/stores that cross cacheline boundaries get split into two memory accesses, causing slowdowns of up to 100% for large 64-byte vectors, while smaller vectors see smaller impacts (around 10-20%). Aligning stores tends to matter more than aligning loads on x64. In the C2 auto-vectorizer, accidentally aligning loads instead of stores caused a 20% performance regression. With the Vector API, alignment is the developer's responsibility since JDK26 gives no way to query array alignment; off-heap MemorySegments allocated with explicit alignment (e.g., 64-byte cacheline) guarantee aligned access, while heap arrays have unpredictable alignment that gets worse with compact object headers enabled. Despite this, vectorization is usually profitable even without perfect alignment.

## Full article

daily.dev links to this article rather than hosting it. Read it at the original source: <https://eme64.github.io/blog/2026/01/12/Alignment-Performance.html>

## Questions this post answers

### Does Java's Vector API let me control the memory alignment of arrays?

No, as of JDK26 there is no way to know or control the alignment of a Java array's payload. Array headers are 8-byte aligned, but the 0th element sits at an offset of 12 or 16 bytes depending on JVM configuration and element type, and the garbage collector can move the array and change its alignment at any time. For guaranteed cacheline alignment, allocate off-heap native memory with Arena.allocate and specify the required alignment.

_Anyone tuning Vector API performance can track JDK alignment behavior changes on daily.dev._

### Why is misaligned store performance worse than misaligned load performance on x64 CPUs?

On x64 machines with AVX512, misaligned stores incur a larger performance penalty than misaligned loads. Benchmarks with 64-byte vectors showed up to a 50% performance difference between best and worst alignment cases, and when only one of load or store can be aligned, aligning the store yields about a 20% better result than aligning the load. This asymmetry caused a real 20% regression in the JDK's C2 auto-vectorizer after the alignment target was accidentally swapped from stores to loads.

_Developers debugging vectorization regressions can follow alignment-related JVM performance fixes on daily.dev._

### How much performance is lost when a SIMD vector access crosses a cacheline boundary?

When a vector load or store crosses a 64-byte cacheline boundary, the CPU splits it into two separate accesses, which can reduce performance by up to 50% to over 100% for large 64-byte vectors on x64 AVX512, since nearly all misaligned large vectors get split. Smaller 8-byte vectors show only about a 20% impact, and on some Aarch64 NEON machines the effect is closer to 10%, because a smaller fraction of accesses actually cross a boundary.

_Engineers weighing vectorization trade-offs can keep up with cacheline alignment benchmarks on daily.dev._

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---

Tags: [#performance](https://daily.dev/tags/performance), [#java](https://daily.dev/tags/java), [#jvm](https://daily.dev/tags/jvm)

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