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description: Alibaba&#x27;s Qwen team is releasing Qwen3.8-Flash-Next, described as a preview built on the upcoming Qwen4 architecture rather than a standalone model. Early...
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# Qwen teases Qwen4 architecture via a surprise Flash-Next drop

**[Trends](https://daily.dev/sources/trends)** · 2 min read · 1 upvotes · 0 comments

## Summary

Alibaba's Qwen team is releasing Qwen3.8-Flash-Next, described as a preview built on the upcoming Qwen4 architecture rather than a standalone model. Early reports suggest roughly 125 billion total parameters in a mixture-of-experts configuration, though activation parameter counts remain unconfirmed. The open-source AI community is treating the drop as a signal of what Qwen4 will bring, with excitement centered more on anticipation than the release itself.

## Content

Alibaba dropped Qwen3.8-Flash-Next and the numbers are genuinely hard to dismiss. It's a 125B MoE model that activates only 6B parameters per token, scores 62.5 on SWE-bench Pro (Claude Opus 4.6 Max sits at 53.4), and costs $0.16/$0.47 per million input/output tokens via API. For context, that's roughly 12x cheaper than Qwen 3.8 Max.

The architecture is the real story here. Alibaba is calling this an early preview of Qwen4, and it ships with a few genuinely unusual choices: a hybrid Gated DeltaNet plus sparse attention scheme that cuts KV cache growth at long contexts, gated residual connections with four branches instead of one, and a 51B-parameter n-gram embedding layer ("engram") designed to be offloaded to regular RAM rather than GPU memory. That last part is a quiet nod to export-control-constrained hardware.

The local-run situation is better than you'd expect for a 125B model. Unsloth has it running on 75GB RAM. On an M5 Max with 128GB unified memory, MLX hits ~60 tokens/sec versus ~30 for llama.cpp. Someone already got a quantized version running on 39GB via MLX-4bit. vLLM has day-zero support on both NVIDIA and AMD. The community is clearly motivated.

Reactions are enthusiastic but not uncritical. One independent benchmark (Kingbench, 8 questions) put it at 70% versus GLM 5.3 Flash's 78.75%, with losses on front-end and 3D polish tasks. More pointed: Alibaba graded at least one benchmark score using GPT-4o rather than the standard grader, which is the kind of footnote that tends to age badly when people start digging.

There's also a licensing question nobody's fully resolved. The model ships under a qwen-community license while Alibaba plans to charge large commercial users. That structure could disqualify it from the EU AI Act's open-source documentation exemption. Whether that matters to most developers right now is another question, but it's worth knowing before you build on it.

The broader vibe: the open-source crowd is excited, the benchmarks are strong enough to take seriously, and the Qwen4 architecture preview framing is doing real work in generating hype. Whether the production Qwen4 delivers on what this preview suggests is the actual bet being made here.

## Questions this post answers

### What is Qwen3.8-Flash-Next and how does it relate to Qwen4?

Qwen3.8-Flash-Next is a preview release from Alibaba's Qwen team built on the new Qwen4 architecture, rather than a standalone model in its own right. Early reports describe it as a mixture-of-experts model with around 125 billion total parameters, though exact activation parameter counts have not been confirmed. It is being treated by the community as an early signal of what Qwen4 will bring.

_Developers evaluating open-source LLM roadmaps can follow Qwen4 architecture details as they emerge on daily.dev._

## Community take

How the wider developer community reacted, aggregated from 4 discussions and 17 comments across x (as of 2026-08-29).

**TL;DR:** Reactions focus mainly on the technical novelty of beating a frontier model with only 6B active parameters and the practical implications of offloading the 51B N-gram table to host RAM, with day-0 tooling support seen as the real enabler for local use.

**Sentiment:** 30% positive · 45% mixed · 25% skeptical

**The case for**

- Beating a frontier model on SWE-bench Pro with just 6B active params is seen as impressive and undercuts active-param-count as a proxy for capability.
- Day-0 support across NVIDIA, AMD, vLLM, and llama.cpp is viewed as what actually makes the model usable rather than just a benchmark headline.
- Some see the offloadable memory architecture as a signal that future large models may rely less heavily on HBM.

**The pushback**

- Some caution that treating the 51B N-gram host-RAM offload as free capacity is a trap in production if context length and memory settings aren't tuned accordingly.
- Open doubts about whether throughput actually holds during long tool-call loops or high context lengths once the table sits in host RAM rather than just single-shot generation.

**By community**

- x (mixed): Excitement over the compute-efficiency claim is tempered by practical questions about real-world throughput and memory offload tradeoffs.

**Hottest debate:** Whether the offloaded 51B N-gram table genuinely delivers claimed performance under real workloads (long tool-call loops, high context) or only in best-case single-shot scenarios.

**Open questions**

- Does throughput hold on long tool-call loops once the N-gram table sits in host RAM, or only on single-shot generation?
- Does keeping the 51B N-gram table in host RAM still deliver the claimed prefill speedup at 1M context, or does async prefetch become a bottleneck?
- Is the Qwen Sparse Attention engine work landing in mainline vLLM or staying limited to the Qwen-specific image?

**Highlights**

> @Hesamation 6B active params clearing a frontier model on SWE-bench Pro. Active params is quietly losing its meaning as a compute proxy.
> — [DoDataThings on x](https://x.com/DoDataThings/status/2092615913111728361)

> @vllm_project @Alibaba_Qwen day-0 with ple cpu offload is the part i care about. does keeping 51b n-gram in host ram still give 7.6x prefill at 1m or does async prefetch bottleneck? everyone on dgx spark vs 3090 is watching
> — [ibesh\_tech on x · 1 points](https://x.com/ibesh_tech/status/2092611079109222484)

> @vllm_project @Alibaba_Qwen Day-0 support is the easy part. The trap in prod is treating the 51B N-gram offload as free capacity. VLLM_PLE_CPU_OFFLOAD=1 saves HBM. It does not save you if: • max_model_len stays at 262K “because it’s native” • gpu_memory_utilization stays aggressive • concurrent tool
> — [pusulainfra on x](https://x.com/pusulainfra/status/2092606721021673907)

> @vllm_project @Alibaba_Qwen The offloadable 51B table is the line that matters for running this locally.  Does throughput hold on long tool-call loops once it sits in host RAM, or only on single-shot generate?
> — [mkeremturhan on x · 1 points](https://x.com/mkeremturhan/status/2092604612276572454)

> @vllm_project @Alibaba_Qwen llama.cpp and vLLM both have day-0 support with a CPU-offload flag for the 51B n-gram table. That was the easy part. vLLM says the real work was Qwen Sparse Attention — the piece you can't offload. The bits you can offload are the ones everyone talks about.
> — [TeqVolt on x](https://x.com/TeqVolt/status/2092609654211625238)

**Source threads**

- [x](https://x.com/Hesamation/status/2092595360606675129) · 1 points · 4 comments
- [x](https://x.com/ClementDelangue/status/2092597106963775821) · 0 points · 0 comments
- [x](https://x.com/vllm_project/status/2092600887873286157) · 0 points · 13 comments
- [x](https://x.com/_akhaliq/status/2092619455226413059) · 0 points · 0 comments

---

Tags: [#open-source](https://daily.dev/tags/open-source), [#llm](https://daily.dev/tags/llm), [#alibaba](https://daily.dev/tags/alibaba), [#qwen](https://daily.dev/tags/qwen), [#mixture-of-experts](https://daily.dev/tags/mixture-of-experts)

[View this post on daily.dev](https://daily.dev/posts/qwen-teases-qwen4-architecture-via-a-surprise-flash-next-drop-betdmnvg2)

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