Researchers demonstrate the first realization of the fermionic ν=1/3 Laughlin state on a digital quantum processor using IonQ's trapped-ion hardware. The team developed an efficient Hamiltonian variational ansatz (HVA) that prepares the state with 369 two-qubit gates on a 16-qubit circuit, leveraging the hierarchical structure of the Laughlin parent Hamiltonian to minimize circuit depth. Key topological signatures were verified directly on hardware, including bulk-edge density structure, correlation holes, and topological entanglement entropy, all showing strong agreement with exact diagonalization benchmarks. Symmetry-verification error mitigation was critical to achieving meaningful results on NISQ hardware. The work establishes an end-to-end workflow for simulating material-intrinsic topological orders on digital quantum processors and opens paths toward exploring non-Abelian topological phases and anyonic excitations.
