--- title: Records Fall for 3D Chip Tech | daily.dev description: Two research teams set new records in hybrid bonding, a 3D chip stacking technology, at the IEEE ECTC conference. Imec and EV Group achieved a wafer-to-wafer... canonical: https://daily.dev/posts/records-fall-for-3d-chip-tech-aoqzhvjwz twitter:card: summary_large_image twitter:site: @dailydotdev og:type: website og:site_name: daily.dev og:title: Records Fall for 3D Chip Tech | daily.dev og:description: Two research teams set new records in hybrid bonding, a 3D chip stacking technology, at the IEEE ECTC conference. Imec and EV Group achieved a wafer-to-wafer... og:url: https://daily.dev/posts/records-fall-for-3d-chip-tech-aoqzhvjwz og:image: https://api.daily.dev/og/posts/AOQZhVJwz.png og:image:alt: Records Fall for 3D Chip Tech og:image:width: 1200 og:image:height: 630 og:locale: en --- > ## Documentation Index > Fetch the complete documentation index at: https://daily.dev/llms.txt > Use this file to discover all available pages before exploring further. # Records Fall for 3D Chip Tech **[IEEE Spectrum](https://daily.dev/sources/ieeespectrum)** · 6 min read · 0 upvotes · 0 comments ## Summary Two research teams set new records in hybrid bonding, a 3D chip stacking technology, at the IEEE ECTC conference. Imec and EV Group achieved a wafer-to-wafer (W2W) bond pitch of 200 nm, down from 250 nm, while CEA-Leti reached a die-to-wafer (D2W) pitch of 1 μm — a 50% reduction from the previous 2 μm record, enabling one million connections per square millimeter. W2W improvements relied on better chemical mechanical polishing and alignment, while D2W progress centered on alignment precision. Separately, Huawei announced a 1.5 μm D2W pitch in its upcoming Kirin processors, a notable step given U.S. export control restrictions. Mass production pitches remain far behind research milestones, and improving yield at finer pitches is the next challenge. ## Full article daily.dev links to this article rather than hosting it. Read it at the original source: ## Similar posts on daily.dev - [Rolled Silicon 3D Chips Could Shrink Circuits](https://daily.dev/posts/rolled-silicon-3d-chips-could-shrink-circuits-1ofqepeb8) · IEEE Spectrum · 0 upvotes · 0 comments - [China just closed a gap in chipmaking that nobody talks about. The wafer size tells you how far it has to go.](https://daily.dev/posts/china-just-closed-a-gap-in-chipmaking-that-nobody-talks-about-the-wafer-size-tells-you-how-far-it-h-py3pkmxpx) · The Next Web · 0 upvotes · 0 comments --- [View this post on daily.dev](https://daily.dev/posts/records-fall-for-3d-chip-tech-aoqzhvjwz) ```json {"@context":"https://schema.org","@graph":[{"@type":"Organization","@id":"https://daily.dev/#organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180},"sameAs":["https://twitter.com/dailydotdev","https://github.com/dailydotdev","https://www.linkedin.com/company/daily-dev-ltd"]},{"@type":"WebSite","@id":"https://daily.dev/#website","url":"https://daily.dev","name":"daily.dev","publisher":{"@id":"https://daily.dev/#organization"},"potentialAction":{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https://daily.dev/search?q={search_term_string}"},"query-input":"required name=search_term_string"}}]} {"@context":"https://schema.org","@type":"TechArticle","headline":"Records Fall for 3D Chip Tech","url":"https://daily.dev/posts/records-fall-for-3d-chip-tech-aoqzhvjwz","mainEntityOfPage":{"@type":"WebPage","@id":"https://daily.dev/posts/records-fall-for-3d-chip-tech-aoqzhvjwz"},"datePublished":"2026-06-25T14:03:17.983Z","dateModified":"2026-06-25T14:13:11.573Z","description":"Two research teams set new records in hybrid bonding, a 3D chip stacking technology, at the IEEE ECTC conference. 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