--- title: RISC-V 101 – what is it and what does it mean for Canonical? description: RISC-V is an open standard instruction set architecture (ISA) that allows anyone to create a CPU implementation. Originally popular in deeply embedded systems,... canonical: https://daily.dev/posts/risc-v-101-what-is-it-and-what-does-it-mean-for-canonical--f8lnd00zt twitter:card: summary_large_image twitter:site: @dailydotdev og:type: website og:site_name: daily.dev og:title: RISC-V 101 – what is it and what does it mean for Canonical? | daily.dev og:description: RISC-V is an open standard instruction set architecture (ISA) that allows anyone to create a CPU implementation. Originally popular in deeply embedded systems,... og:url: https://daily.dev/posts/risc-v-101-what-is-it-and-what-does-it-mean-for-canonical--f8lnd00zt og:image: https://api.daily.dev/og/posts/f8LND00Zt.png og:image:alt: RISC-V 101 – what is it and what does it mean for Canonical? og:image:width: 1200 og:image:height: 630 og:locale: en --- > ## Documentation Index > Fetch the complete documentation index at: https://daily.dev/llms.txt > Use this file to discover all available pages before exploring further. # RISC-V 101 – what is it and what does it mean for Canonical? **[Ubuntu](https://daily.dev/sources/ubuntu)** · 6 min read · 1 upvotes · 0 comments ## Summary RISC-V is an open standard instruction set architecture (ISA) that allows anyone to create a CPU implementation. Originally popular in deeply embedded systems, 2026 is expected to bring a surge of Linux-capable RISC-V development boards. Key advantages include permissive licensing enabling diverse business models, extensibility for AI/ML and custom accelerators, and growing software ecosystem support (Linux kernel, GCC, LLVM). Canonical has supported RISC-V since 2021, treats it as a first-class architecture, and plans to support the RVA23 profile from Ubuntu 25.10 onwards with up to 15 years of LTS support via Ubuntu Pro. ## Full article daily.dev links to this article rather than hosting it. Read it at the original source: ## Similar posts on daily.dev - [RISC-V profiles – why is RVA23 significant?](https://daily.dev/posts/risc-v-profiles-why-is-rva23-significant--t8tx0wdyq) · Ubuntu · 0 upvotes · 0 comments - [Canonical Talks Up RISC-V This Year With Ubuntu 26.04 LTS](https://daily.dev/posts/canonical-talks-up-risc-v-this-year-with-ubuntu-26-04-lts-1rng9fdfq) · Phoronix · 0 upvotes · 0 comments - [The AI Shift: Why RISC-V is poised to challenge Arm and x86](https://daily.dev/posts/the-ai-shift-why-risc-v-is-poised-to-challenge-arm-and-x86-6dds9fta4) · The New Stack · 0 upvotes · 0 comments - [Canonical and Ubuntu RISC-V: a 2025 retro and looking forward to 2026](https://daily.dev/posts/canonical-and-ubuntu-risc-v-a-2025-retro-and-looking-forward-to-2026-nadfdbivo) · Ubuntu · 0 upvotes · 0 comments --- Tags: [#linux](https://daily.dev/tags/linux), [#ubuntu](https://daily.dev/tags/ubuntu) [View this post on daily.dev](https://daily.dev/posts/risc-v-101-what-is-it-and-what-does-it-mean-for-canonical--f8lnd00zt) ```json {"@context":"https://schema.org","@graph":[{"@type":"Organization","@id":"https://daily.dev/#organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180},"sameAs":["https://twitter.com/dailydotdev","https://github.com/dailydotdev","https://www.linkedin.com/company/daily-dev-ltd"]},{"@type":"WebSite","@id":"https://daily.dev/#website","url":"https://daily.dev","name":"daily.dev","publisher":{"@id":"https://daily.dev/#organization"},"potentialAction":{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https://daily.dev/search?q={search_term_string}"},"query-input":"required name=search_term_string"}}]} {"@context":"https://schema.org","@type":"TechArticle","headline":"RISC-V 101 – what is it and what does it mean for Canonical?","url":"https://daily.dev/posts/risc-v-101-what-is-it-and-what-does-it-mean-for-canonical--f8lnd00zt","mainEntityOfPage":{"@type":"WebPage","@id":"https://daily.dev/posts/risc-v-101-what-is-it-and-what-does-it-mean-for-canonical--f8lnd00zt"},"datePublished":"2026-04-07T22:18:31.568Z","dateModified":"2026-04-07T22:19:00.659Z","description":"RISC-V is an open standard instruction set architecture (ISA) that allows anyone to create a CPU implementation. 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