RISC-V is now officially recognized as a tier 3 supported platform for CPython, following months of community work testing on real hardware, fixing architecture-specific bugs, and improving build support. The RISE Project provided RISC-V buildbot machines, and contributors including Ludovic Henry, Furkan Onder, and Emma Smith drove the effort, supported by the Sovereign Tech Agency. Next steps include integrating RISC-V into CPython's CI via RISE's RISC-V Runners initiative, pursuing tier 2 status, and exploring architecture-specific performance optimizations. Users with RISC-V hardware are encouraged to test builds and report issues.
Questions this post answers
Is RISC-V officially supported by CPython now?
Yes, RISC-V is now officially supported by CPython as a tier 3 platform under PEP 11. This follows extended community work including real-hardware testing, architecture-specific bug fixes, and build improvements, with the RISE Project providing dedicated RISC-V buildbot machines for ongoing testing. daily.dev helps developers porting or testing Python on new architectures track platform support changes like this.
What does tier 3 platform support mean for CPython?
Tier 3 support in CPython's PEP 11 means a platform has official buildbots that must pass before a release, but failures do not block releases the way tier 1 or tier 2 failures would. RISC-V just reached this status, with plans to eventually pursue tier 2 support and bring RISC-V testing directly into CPython's CI for faster contributor feedback. developers tracking platform tiers for CPython can follow changes like this through daily.dev.
Who supported RISC-V hardware testing for CPython development?
The RISE Project supplied several RISC-V machines used as buildbots for CPython testing and architecture-specific debugging. Key contributors included Ludovic Henry from RISE, Furkan Onder, and Emma Smith, with the effort also backed by a Sovereign Tech Agency fellowship supporting the work. daily.dev keeps developers following open-source infrastructure efforts like RISC-V hardware testing in one place.