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title: RVA23 vs ARMv9 a Small Experiment | daily.dev
description: An experiment compares RISC-V&#x27;s RVA22/RVA23 profiles against ARMv9 by compiling the chibicc C compiler with itself, excluding SIMD to isolate base ISA effects....
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og:description: An experiment compares RISC-V&#x27;s RVA22/RVA23 profiles against ARMv9 by compiling the chibicc C compiler with itself, excluding SIMD to isolate base ISA effects....
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# RVA23 vs ARMv9 a Small Experiment

**[Lobsters](https://daily.dev/sources/lobsters)** · 5 min read · 0 upvotes · 0 comments

## Summary

An experiment compares RISC-V's RVA22/RVA23 profiles against ARMv9 by compiling the chibicc C compiler with itself, excluding SIMD to isolate base ISA effects. RISC-V binaries are about 18% smaller and RVA23 fetches 24% fewer bytes than ARMv9, but ARM decodes about 6.5% fewer instructions on average. After accounting for ARM's micro-op cracking of complex addressing modes, both ISAs end up with roughly similar uop counts. GEM5 simulation shows both RVA22 and RVA23 executing faster than ARMv9 in this workload, though the difference between RVA22 and RVA23 themselves is negligible since RVV vector support was disabled.

## Full article

daily.dev links to this article rather than hosting it. Read it at the original source: <https://gist.github.com/camel-cdr/3a7aed17e017e8cab675ad696c7d14af>

## Questions this post answers

### How does RISC-V RVA23 code density compare to ARMv9 for the same workload?

RVA23 binaries fetch about 24% fewer bytes than ARMv9 when compiling chibicc with itself, excluding SIMD instructions from both ISAs. Static binary size is also about 18% smaller for RISC-V than ARM. However, ARM decodes roughly 6.5% fewer instructions on average because RISC-V lacks ARM's complex addressing modes.

_Comparing ISA tradeoffs like these is easier when engineering benchmarks surface directly to daily.dev readers._

### Why does ARM need more micro-operations (uops) than its instruction count suggests?

ARM's complex addressing modes, such as load/store pairs and pre-/post-index load/stores, get cracked into multiple uops by the CPU backend. Using the Apple Silicon CPU Optimization Guide's cracking rules, adjusting for uops shows ARM and RISC-V end up with roughly the same total uop count on clang, and RISC-V even has fewer uops on GCC.

_Developers weighing ARM versus RISC-V performance can track these microarchitecture nuances on daily.dev._

### Does the RISC-V RVA23 profile perform better than RVA22 in real workloads?

The difference between RVA22 and RVA23 is negligible for compiling the chibicc compiler with SIMD/RVV support disabled, since RVV vector support is the biggest addition in RVA23 and was excluded from testing. Both profiles executed faster than ARMv9 in GEM5 simulation, with clang oddly performing worse under RVA23 than RVA22.

_Engineers evaluating RISC-V profile upgrades can follow benchmark deep-dives like this on daily.dev._

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---

Tags: [#architecture](https://daily.dev/tags/architecture), [#arm](https://daily.dev/tags/arm)

[View this post on daily.dev](https://daily.dev/posts/rva23-vs-armv9-a-small-experiment-wmj4ts8di)

```json
{"@context":"https://schema.org","@graph":[{"@type":"Organization","@id":"https://daily.dev/#organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180},"sameAs":["https://twitter.com/dailydotdev","https://github.com/dailydotdev","https://www.linkedin.com/company/daily-dev-ltd"]},{"@type":"WebSite","@id":"https://daily.dev/#website","url":"https://daily.dev","name":"daily.dev","publisher":{"@id":"https://daily.dev/#organization"},"potentialAction":{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https://daily.dev/search?q={search_term_string}"},"query-input":"required name=search_term_string"}}]}
{"@context":"https://schema.org","@type":"TechArticle","headline":"RVA23 vs ARMv9 a Small Experiment","url":"https://daily.dev/posts/rva23-vs-armv9-a-small-experiment-wmj4ts8di","mainEntityOfPage":{"@type":"WebPage","@id":"https://daily.dev/posts/rva23-vs-armv9-a-small-experiment-wmj4ts8di"},"datePublished":"2026-08-15T22:34:32.377Z","dateModified":"2026-08-15T22:34:56.727Z","description":"An experiment compares RISC-V's RVA22/RVA23 profiles against ARMv9 by compiling the chibicc C compiler with itself, excluding SIMD to isolate base ISA effects....","image":"https://media.daily.dev/image/upload/f_auto,q_auto/v1/posts/e1243c1243ed74cc7f9615599f65ad74?_a=AQAEuop","thumbnailUrl":"https://media.daily.dev/image/upload/f_auto,q_auto/v1/posts/e1243c1243ed74cc7f9615599f65ad74?_a=AQAEuop","isAccessibleForFree":true,"articleSection":"Lobsters","inLanguage":"en","publisher":{"@type":"Organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180}},"author":{"@type":"Organization","name":"Lobsters","logo":"https://media.daily.dev/image/upload/s--tl8v_Fku--/f_auto,t_logo/v1698841318/logos/lobste.jpg","url":"https://daily.dev/sources/lobsters"},"commentCount":0,"discussionUrl":"https://daily.dev/posts/rva23-vs-armv9-a-small-experiment-wmj4ts8di","interactionStatistic":[{"@type":"InteractionCounter","interactionType":{"@type":"LikeAction"},"userInteractionCount":0},{"@type":"InteractionCounter","interactionType":{"@type":"CommentAction"},"userInteractionCount":0}],"keywords":"architecture,arm","timeRequired":"PT5M"}
{"@context":"https://schema.org","@type":"BreadcrumbList","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https://daily.dev"},{"@type":"ListItem","position":2,"name":"Lobsters","item":"https://daily.dev/sources/lobsters"},{"@type":"ListItem","position":3,"name":"RVA23 vs ARMv9 a Small Experiment"}]}
{"@context":"https://schema.org","@type":"FAQPage","@id":"https://daily.dev/posts/rva23-vs-armv9-a-small-experiment-wmj4ts8di#faq","mainEntity":[{"@type":"Question","name":"How does RISC-V RVA23 code density compare to ARMv9 for the same workload?","acceptedAnswer":{"@type":"Answer","text":"RVA23 binaries fetch about 24% fewer bytes than ARMv9 when compiling chibicc with itself, excluding SIMD instructions from both ISAs. Static binary size is also about 18% smaller for RISC-V than ARM. However, ARM decodes roughly 6.5% fewer instructions on average because RISC-V lacks ARM's complex addressing modes. Comparing ISA tradeoffs like these is easier when engineering benchmarks surface directly to daily.dev readers."}},{"@type":"Question","name":"Why does ARM need more micro-operations (uops) than its instruction count suggests?","acceptedAnswer":{"@type":"Answer","text":"ARM's complex addressing modes, such as load/store pairs and pre-/post-index load/stores, get cracked into multiple uops by the CPU backend. Using the Apple Silicon CPU Optimization Guide's cracking rules, adjusting for uops shows ARM and RISC-V end up with roughly the same total uop count on clang, and RISC-V even has fewer uops on GCC. Developers weighing ARM versus RISC-V performance can track these microarchitecture nuances on daily.dev."}},{"@type":"Question","name":"Does the RISC-V RVA23 profile perform better than RVA22 in real workloads?","acceptedAnswer":{"@type":"Answer","text":"The difference between RVA22 and RVA23 is negligible for compiling the chibicc compiler with SIMD/RVV support disabled, since RVV vector support is the biggest addition in RVA23 and was excluded from testing. Both profiles executed faster than ARMv9 in GEM5 simulation, with clang oddly performing worse under RVA23 than RVA22. Engineers evaluating RISC-V profile upgrades can follow benchmark deep-dives like this on daily.dev."}}]}
```

