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title: Sorter | daily.dev
description: A detailed walkthrough of building a bitonic sorting network circuit in Lava, a Haskell-embedded hardware description language, using butterfly networks and...
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> ## Documentation Index
> Fetch the complete documentation index at: https://daily.dev/llms.txt
> Use this file to discover all available pages before exploring further.

# Sorter

**[Awesome Java Newsletter](https://daily.dev/sources/java_libhunt)** · 7 min read · 0 upvotes · 0 comments

## Summary

A detailed walkthrough of building a bitonic sorting network circuit in Lava, a Haskell-embedded hardware description language, using butterfly networks and combinators like riffle, unriffle, ilv, evens, and bfly. The design is recursively constructed from two-sorters into mergers and full sorters, with example layouts for 8, 16, and 32 input sorters synthesized on Xilinx Virtex-II FPGAs, including real performance figures (165MHz on an XC2V3000 with 14-cycle latency) and hardware verification via ChipScope.

## Full article

daily.dev links to this article rather than hosting it. Read it at the original source: <https://raintown.org/lava/sorter>

## Questions this post answers

### How do you build a hardware sorting network using butterfly networks in Lava?

A sorting network in Lava is built recursively: a sorter of degree n uses two smaller sorters, reverses the upper sort's output, then merges both using a butterfly of two-sorters (bfly). The butterfly itself is built from combinators like riffle, unriffle, ilv (interleave), and evens, composing two-element sorters into a bitonic merger that handles any power-of-two input size.

_Developers exploring hardware description languages can track deep dives like this sorting network design on daily.dev._

### What performance does a 32-input bitonic sorting network achieve on a Xilinx FPGA?

A 32-input network sorting 16-bit numbers each clock tick runs at 165MHz on a Xilinx XC2V3000 part, with a latency of 14 clock ticks, built using version 4.1i of the Xilinx design tools. Larger datasets beyond this size can be sorted by storing numbers in BlockRAM and iteratively sorting and merging.

_Engineers benchmarking FPGA sorting circuits can follow similar hardware design deep dives on daily.dev._

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---

Tags: [#haskell](https://daily.dev/tags/haskell), [#fpga](https://daily.dev/tags/fpga)

[View this post on daily.dev](https://daily.dev/posts/sorter-ti2vetkxl)

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