ROCm now supports SPIR-V as a portable intermediate representation for AMD GPUs, enabling a compile-once, specialize-on-device model. Instead of building separate native code objects for each GPU architecture (which causes linear growth in build time and binary size), developers can target the abstract `amdgcnspirv` target and let the runtime JIT-compile to the actual device ISA on first launch. A key innovation is Zero-Cost Feature Selection (ZCFS): late-resolved feature predicates like `__builtin_amdgcn_processor_is` and `__builtin_amdgcn_is_invocable` are folded during SPIR-V→native lowering so exactly one branch survives per architecture with no runtime overhead. Benchmarks on MI350X (CDNA4) show flat compile time and binary size regardless of target count, forward compatibility with GPUs not yet released at build time, and steady-state performance matching native code after a one-time ~70–100ms JIT cost on first launch. The main current limitation is partial SPIR-V support in ROCm's per-arch device libraries (rocBLAS, Composable Kernel, rocFFT in progress).
