--- title: Unlocking Tensor Core Performance for Machine Learning... description: Researchers tested Tensor Core FP32 emulation methods on the Point Edge Transformer (PET) machine learning interatomic potential, finding they speed up... canonical: https://daily.dev/posts/unlocking-tensor-core-performance-for-machine-learning-interatomic-potentials-c3xgieaqo twitter:card: summary_large_image twitter:site: @dailydotdev og:type: website og:site_name: daily.dev og:title: Unlocking Tensor Core Performance for Machine Learning Interatomic Potentials | daily.dev og:description: Researchers tested Tensor Core FP32 emulation methods on the Point Edge Transformer (PET) machine learning interatomic potential, finding they speed up... og:url: https://daily.dev/posts/unlocking-tensor-core-performance-for-machine-learning-interatomic-potentials-c3xgieaqo og:image: https://api.daily.dev/og/posts/c3xgieAQO.png og:image:alt: Unlocking Tensor Core Performance for Machine Learning Interatomic Potentials og:image:width: 1200 og:image:height: 630 og:locale: en --- > ## Documentation Index > Fetch the complete documentation index at: https://daily.dev/llms.txt > Use this file to discover all available pages before exploring further. # Unlocking Tensor Core Performance for Machine Learning Interatomic Potentials **[NVIDIA Developer](https://daily.dev/sources/nvidiadev)** · 10 min read · 0 upvotes · 0 comments ## Summary Researchers tested Tensor Core FP32 emulation methods on the Point Edge Transformer (PET) machine learning interatomic potential, finding they speed up molecular dynamics while retaining behavior close to FP32. BF16x9 on Blackwell GPUs sped up large GEMMs by 2.2 to 2.5x and full MD steps by up to 1.7x, with error below the model's own non-determinism. TF32x3 on A100 GPUs accelerated GEMMs by 1.7 to 1.9x and MD steps by up to 1.5x. In structural relaxation tests, TF32x3 matched FP32 convergence at 218 to 222 steps, while a cruder one-pass TF32 approach failed to converge within 500 steps. ## Full article daily.dev links to this article rather than hosting it. Read it at the original source: ## Questions this post answers ### What is the TF32x3 method and how does it speed up FP32 matrix multiplication on NVIDIA Ampere GPUs? TF32x3 represents each FP32 operand as a leading TF32 component and a residual TF32 component, then evaluates three cross-products (leading-by-leading and two leading-by-residual) on Tensor Cores with FP32 accumulation, omitting the smallest residual-by-residual term. NVIDIA CUTLASS implements this via the OpMultiplyAddFastF32 operator, accelerating GEMMs on A100 by about 1.7 to 1.9x without retraining. _Developers tuning scientific workloads for GPU throughput can track Tensor Core precision techniques like this on daily.dev._ ### Does using lower-precision Tensor Core math (like TF32x3) hurt accuracy in molecular dynamics simulations? No, in tests on the PET interatomic potential, TF32x3 preserved potential-energy smoothness and energy conservation comparable to native FP32, and matched FP32's structural relaxation convergence at 218 to 222 steps versus FP32's 218 steps. A cruder one-pass TF32 approach, by contrast, showed energy drift and failed to converge within 500 steps. _Teams weighing speed against numerical accuracy in GPU-accelerated simulations can follow results like these on daily.dev._ ### How do I enable BF16x9 Tensor Core acceleration for FP32 matrix multiplication in cuBLAS without changing my model code? Set the environment variable CUBLAS_EMULATE_SINGLE_PRECISION=1 (or use the CUBLAS_COMPUTE_32F_EMULATED_16BFX9 compute type) on Blackwell GPUs with compute capability 10.0 or 10.3. This decomposes each FP32 operand into three BF16 components and recombines nine pairwise products in FP32, requiring no retraining or architecture changes, and accelerated large GEMMs by 2.2 to 2.5x in testing. _Engineers squeezing more throughput from Blackwell GPUs can keep up with cuBLAS precision tricks like this on daily.dev._ ## Similar posts on daily.dev - [Using NVFP4 Low-Precision Model Training for Higher Throughput Without Losing Accuracy](https://daily.dev/posts/using-nvfp4-low-precision-model-training-for-higher-throughput-without-losing-accuracy-mburtmoay) · NVIDIA Developer · 1 upvotes · 0 comments - [Enabling Up to 41% Faster Pre-training: MXFP8 and DeepEP for DeepSeek-V3 on B200 with TorchTitan – PyTorch](https://daily.dev/posts/enabling-up-to-41-faster-pre-training-mxfp8-and-deepep-for-deepseek-v3-on-b200-with-torchtitan-p-xgwnngegk) · PyTorch · 0 upvotes · 0 comments - [GPU-unlock: FP/BF16 instruction issue rate on Nvidia 3000's cards](https://daily.dev/posts/gpu-unlock-fp-bf16-instruction-issue-rate-on-nvidia-3000-s-cards-kbbkhu5nr) · Hacker News · 2 upvotes · 0 comments - [Breaking the Hardware Barrier: Software FP8 for Older GPUs](https://daily.dev/posts/breaking-the-hardware-barrier-software-fp8-for-older-gpus-iceioy3uy) · Towards Data Science · 1 upvotes · 0 comments - [I tried three ways to train my own ChatGPT on Nvidia DGX Sparks, and only one made it faster](https://daily.dev/posts/i-tried-three-ways-to-train-my-own-chatgpt-on-nvidia-dgx-sparks-and-only-one-made-it-faster-hz7mpkxdr) · XDA Developers · 0 upvotes · 0 comments --- Tags: [#machine-learning](https://daily.dev/tags/machine-learning), [#nvidia](https://daily.dev/tags/nvidia), [#cuda](https://daily.dev/tags/cuda) [View this post on daily.dev](https://daily.dev/posts/unlocking-tensor-core-performance-for-machine-learning-interatomic-potentials-c3xgieaqo) ```json {"@context":"https://schema.org","@graph":[{"@type":"Organization","@id":"https://daily.dev/#organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180},"sameAs":["https://twitter.com/dailydotdev","https://github.com/dailydotdev","https://www.linkedin.com/company/daily-dev-ltd"]},{"@type":"WebSite","@id":"https://daily.dev/#website","url":"https://daily.dev","name":"daily.dev","publisher":{"@id":"https://daily.dev/#organization"},"potentialAction":{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https://daily.dev/search?q={search_term_string}"},"query-input":"required name=search_term_string"}}]} {"@context":"https://schema.org","@type":"TechArticle","headline":"Unlocking Tensor Core Performance for Machine Learning Interatomic Potentials","url":"https://daily.dev/posts/unlocking-tensor-core-performance-for-machine-learning-interatomic-potentials-c3xgieaqo","mainEntityOfPage":{"@type":"WebPage","@id":"https://daily.dev/posts/unlocking-tensor-core-performance-for-machine-learning-interatomic-potentials-c3xgieaqo"},"datePublished":"2026-10-29T15:09:01.003Z","dateModified":"2026-10-29T15:23:02.561Z","description":"Researchers tested Tensor Core FP32 emulation methods on the Point Edge Transformer (PET) machine learning interatomic potential, finding they speed up...","image":"https://media.daily.dev/image/upload/f_auto,q_auto/v1/posts/c632f93c3d711b966ebc703a7b793b5d?_a=AQAEuop","thumbnailUrl":"https://media.daily.dev/image/upload/f_auto,q_auto/v1/posts/c632f93c3d711b966ebc703a7b793b5d?_a=AQAEuop","isAccessibleForFree":true,"articleSection":"NVIDIA Developer","inLanguage":"en","publisher":{"@type":"Organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180}},"author":{"@type":"Organization","name":"NVIDIA Developer","logo":"https://media.daily.dev/image/upload/t_logo,f_auto/v1/logos/86e45aab42ba48ce83103d01b1119910","url":"https://daily.dev/sources/nvidiadev"},"commentCount":0,"discussionUrl":"https://daily.dev/posts/unlocking-tensor-core-performance-for-machine-learning-interatomic-potentials-c3xgieaqo","interactionStatistic":[{"@type":"InteractionCounter","interactionType":{"@type":"LikeAction"},"userInteractionCount":0},{"@type":"InteractionCounter","interactionType":{"@type":"CommentAction"},"userInteractionCount":0}],"keywords":"machine-learning,nvidia,cuda","timeRequired":"PT10M"} {"@context":"https://schema.org","@type":"BreadcrumbList","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https://daily.dev"},{"@type":"ListItem","position":2,"name":"NVIDIA Developer","item":"https://daily.dev/sources/nvidiadev"},{"@type":"ListItem","position":3,"name":"Unlocking Tensor Core Performance for Machine Learning Interatomic Potentials"}]} {"@context":"https://schema.org","@type":"FAQPage","@id":"https://daily.dev/posts/unlocking-tensor-core-performance-for-machine-learning-interatomic-potentials-c3xgieaqo#faq","mainEntity":[{"@type":"Question","name":"What is the TF32x3 method and how does it speed up FP32 matrix multiplication on NVIDIA Ampere GPUs?","acceptedAnswer":{"@type":"Answer","text":"TF32x3 represents each FP32 operand as a leading TF32 component and a residual TF32 component, then evaluates three cross-products (leading-by-leading and two leading-by-residual) on Tensor Cores with FP32 accumulation, omitting the smallest residual-by-residual term. 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