Cadence Design Systems unveiled its Level 5 ChipStack AI Super Agent at Computex 2026, claiming it is the industry's first fully autonomous AI design engineer for chip design. Built on Cadence's EDA portfolio with Nvidia Nemotron models and secured by Nvidia OpenShell runtime, the system manages entire RTL validation and iteration cycles autonomously. In a Computex demonstration, the agent orchestrated hundreds of parallel simulations using Xcelium and Jasper Formal Verification, delivering a claimed 40× acceleration in RTL validation — compressing five weeks of engineering effort to under a day. Unlike Level 4, where engineers interpret results and decide next steps, Level 5 handles loop-level reasoning, automated debug, bug patching, and coverage closure, escalating to humans only when it detects fundamental issues. Engineers shift toward defining design intent, reviewing proposed patches, and making final sign-off decisions. Early access for select partners is planned for the second half of 2026.
