--- title: Why Micron Is Suddenly Ditching 4F² DRAM as Rivals... description: Micron is abandoning 4F² DRAM cell geometry after more than two decades of research, choosing to stick with 6F² instead. Samsung, SK hynix, and CXMT are all... canonical: https://daily.dev/posts/why-micron-is-suddenly-ditching-4f-dram-as-rivals-double-down-4haigbuoi twitter:card: summary_large_image twitter:site: @dailydotdev og:type: website og:site_name: daily.dev og:title: Why Micron Is Suddenly Ditching 4F² DRAM as Rivals Double Down | daily.dev og:description: Micron is abandoning 4F² DRAM cell geometry after more than two decades of research, choosing to stick with 6F² instead. Samsung, SK hynix, and CXMT are all... og:url: https://daily.dev/posts/why-micron-is-suddenly-ditching-4f-dram-as-rivals-double-down-4haigbuoi og:image: https://api.daily.dev/og/posts/4hAIGBUOi.png og:image:alt: Why Micron Is Suddenly Ditching 4F² DRAM as Rivals Double Down og:image:width: 1200 og:image:height: 630 og:locale: en --- > ## Documentation Index > Fetch the complete documentation index at: https://daily.dev/llms.txt > Use this file to discover all available pages before exploring further. # Why Micron Is Suddenly Ditching 4F² DRAM as Rivals Double Down **[Hacker News](https://daily.dev/sources/hn)** · 4 min read · 0 upvotes · 0 comments ## Summary Micron is abandoning 4F² DRAM cell geometry after more than two decades of research, choosing to stick with 6F² instead. Samsung, SK hynix, and CXMT are all moving ahead with 4F² designs, with CXMT claiming server DDR5 RDIMMs by year end. Micron's President and CTO Scott DeBoer says density is actually set by capacitor spacing, not cell footprint, so 4F² adds cost and complexity without much density gain. Micron will instead push 6F² scaling through 1-delta, 1-epsilon, zeta and eta, while betting its long-term future on 3D DRAM, stacking cells vertically rather than shrinking planar geometry. ## Full article daily.dev links to this article rather than hosting it. Read it at the original source: ## Questions this post answers ### why is Micron not adopting 4F² DRAM like Samsung and SK hynix Micron's President and CTO Scott DeBoer says DRAM density is actually limited by the spacing needed for capacitors, not by the nominal cell footprint, so shrinking from 6F² to 4F² doesn't gain much real density while drastically increasing cost and complexity. Despite inventing 4F² and researching it for over two decades, Micron is sticking with 6F² and betting on 3D DRAM instead. _Following memory architecture trade-offs like 6F² versus 4F² DRAM gets easier when you track the roadmap on daily.dev._ ### what is 3D DRAM and how is it different from 3D NAND flash 3D DRAM stacks multiple physical layers of DRAM storage cells vertically, unlike 3D NAND flash which has used simple charge-trap transistors stacked like skyscraper floors for over a decade. DRAM cells are dynamic, each bit needs a delicate, high-aspect-ratio capacitor paired with a transistor that leaks charge, so stacking vertically without thermal crosstalk or signal destruction requires a full overhaul of DRAM architecture. _Developers tracking where memory hardware is headed can follow 3D DRAM progress on daily.dev._ ### which companies are pursuing 4F² DRAM technology Samsung, SK hynix, and CXMT are all moving ahead with 4F² DRAM designs, while Micron has chosen to abandon the approach. CXMT in particular claims it will have 4F² RAM in server DDR5 RDIMMs by the end of the year, positioning it ahead of rivals if the technology proves commercially viable. _Anyone comparing memory vendors' roadmaps can keep an eye on DRAM technology shifts via daily.dev._ ## Community take How the wider developer community reacted, aggregated from 1 discussion and 19 comments across hackernews (as of 2026-10-27). **TL;DR:** Discussion centers on whether Micron's pivot is sound engineering judgment or investor-facing spin for a company that has fallen behind on 4F² scaling, with several technical explanations of the 4F²/6F²/8F² cell geometry differences adding useful context. **Sentiment:** 10% positive · 55% mixed · 35% skeptical **The case for** - Some argue Micron's reasoning is sound: 6F² scaling keeps per-wafer costs low while 3D stacking is a more promising long-term bet. - One commenter frames it as prudent risk management given Micron's deep insight into DRAM supply/demand cycles and oversupply risk. - Micron is seen by some as technically strong, having a track record of delivering performant DRAM without extra manufacturing complexity. **The pushback** - Many suspect this is spin to reframe falling behind competitors as a deliberate strategic choice for investors. - Skeptics question why a company would publicly reveal strategy right before rivals ship a potentially superior technology. - Some see it as a case of the innovator's dilemma, where current profitable production lines discourage investment in unproven new tech. - Doubts raised about whether the capacitor-spacing cost argument is genuinely correct versus a convenient justification. **By community** - hackernews (mixed): Commenters are split between viewing the move as sensible engineering/business strategy and suspecting it's investor-facing spin for a company lagging on next-gen DRAM tech. **Hottest debate:** Whether Micron's 4F² exit is genuine engineering foresight or a cover story for having fallen behind competitors. **Open questions** - Is Micron's claim that capacitor spacing, not cell footprint, limits density actually correct compared to rivals' opposing claims? - Will Micron's 3D DRAM bet pay off or end up like other abandoned memory technologies such as RDRAM? - How much is the decision driven by rowhammer-related reliability concerns at smaller 4F² feature sizes? **Highlights** > Those are completely misleading, because they are not the true cell layouts. Searching for the Micron patent on 6F^2 cells (US 6,975,531) is much more informative. The essence of the problem is the following. An ideal memory array cell is formed at the intersection of a vertical line with a horizontal line. A line has the width 2F (i.e. metal width + spacing width), so the area of the cell is 2F * 2F = 4F^2. Instead of that, most DRAM cells are at the intersection of 2 horizontal lines with 1 vertical line. The single line is a bidirectional data line with the value of the stored bit, while the pair of lines are a write select line and a read select line. Using separate read and write transistors provides better performance. The naive layout for a cell where 2 lines intersect with 1 line has an area of 2F * 4F = 8F^2. An optimized layout where many parts are stacked one over the other and where some lines are shared by adjacent cells, so the spacings are omitted, can have the smaller area of 2F * 3F = 6F^2. In the 6F^2 cell, there are are 3 transistors, but they have the drain stacked over the source and one transistor is stacked above another, to minimize area. To make a 4F^2 DRAM cell, there are various approaches, e.g. one could try to stack even more components vertically or one could go back to one-transistor cells, but in modern technology, but it is not obvious whether the much higher processing cost is compensated by the reduced die area. Micron claims that despite the reduced area the cost would be higher, while the competitors, including the Chinese, claim the opposite. > — [adrian\_b on hackernews](https://news.ycombinator.com/item?id=50262204) > Sounds like innovator's dilemma to me. Their current production lines might be too profitable[0], so diverting expansion capacity to a yet unproven technology (to Micron's to-date profit margin requirements) might be too big of a financial hit. Since they're the ones who came up with 4F design, they must hold a ton of patents on the various incremental improvements. At which point, from a purely cynical and utilitarian view, it would make financial sense to let other players polish the remaining 20% and use patent portfolio as a wedge for mid-term technology transfers. Or in short: "let others figure out the technical complexities and surrounding economics." - Which would make sense from a company that believes they can catch up once the expensive leg of the manufacturing/scaling research has been completed. Whether that bet is good or not, we'll see. 0: Didn't we read a few days ago here that all of 2027 production capacity has been sold out already? > — [bostik on hackernews · 1 comments](https://news.ycombinator.com/item?id=50263161) > Given that the stated plan of Micron is to focus on 3D scaling, keeping per-mm^2 production costs low makes perfect sense. When Samsung introduced their first volume V-NAND flash, the 2D feature sizes were larger than leading edge NAND flash because of the tolerances inherent in producing 90 layer flash (aspect ratio matters!) as well as the cost of production equipment. That trend has continued as it is cheaper to produce flash with more layers than to compensate for difficulties arising from decreasing amounts of charge kept in ever smaller cells. In layperson DRAM-speak this translates to the following: rowhammer attacks are mitigated at the hardware level by increasing the size of and spacing between adjacent cells. At some point further feature size scaling makes it no longer be possible to produce 4F cells that are sufficiently robust against rowhammer type attacks to meet Micron's internal reliability targets. This would be akin to when Intel hit the power wall with the Pentium 4 in the early '00s forcing a change in engineering direction away from merely scaling clock speed. With Micron's insight into the DRAM order pipeline, management likely has to factor in the chance of oversupply in the next couple of years as significant, which makes the shift in direction even more sensible. DRAM price crashes are a regular occurrence in the industry which lead to anti-dumping tariffs and legal battle in the 1990s (as well as Intel's shift away from DRAM towards complex logic devices in 1985). I'm pretty sure Micron's management is consciously working to avoid a repeat of that protracted legal battle. I'd rather have an engineering problem over a legal problem any day of the week. > — [bcrl on hackernews](https://news.ycombinator.com/item?id=50265232) > Sounds rather more like a company behind the innovation curve pretending to "skip" the innovation as if to jump into a better innovation. When the actual truth is they are sticking with the old thing. Reframed as a choice. If "Ditching 4f" is such a good idea, why show their hand right before their competitors make the foolish choice of releasing it? Why not hold your cards until afterwards? Unless perhaps this isn't a brilliant strategy but instead a spin for the investors? > — [Danieru on hackernews · 5 comments](https://news.ycombinator.com/item?id=50261436) > > that does not justify dropping the future innovation Looks like they have mapped the possible paths and consider it a dead end. The density increase is low compared to the effort to process cost, so they just opted for a simpler process with a similar density at a much lower cost per wafer. They might come back to it at some point - they invented it and have substantial IP investment on it. Also, there might be some cost of opportunity - the AI bubble is now, so anything that diverts from current extremely profitable product lines is a terrible idea. It’s a bubble and they have the fiduciary duty to suck it until it’s dry. > — [rbanffy on hackernews · 1 comments](https://news.ycombinator.com/item?id=50264901) **Source threads** - [hackernews](https://news.ycombinator.com/item?id=50245014) · 120 points · 19 comments ## Similar posts on daily.dev - [China’s biggest memory maker says it has caught up with Samsung and Micron](https://daily.dev/posts/china-s-biggest-memory-maker-says-it-has-caught-up-with-samsung-and-micron-0khkuz2wl) · The Next Web · 0 upvotes · 0 comments - [Micron Develops Ultra-Dense 512-GB DDR5 Memory Module](https://daily.dev/posts/micron-develops-ultra-dense-512-gb-ddr5-memory-module-nwc1w1p3l) · Embedded.com · 0 upvotes · 0 comments - [China’s cut-rate DRAM tests Samsung, SK in HBM4 race](https://daily.dev/posts/china-s-cut-rate-dram-tests-samsung-sk-in-hbm4-race-qr4gfnn7r) · Hacker News · 0 upvotes · 0 comments - [We thought Chinese companies could save us from the DRAM crisis, but they're charging just as much as the big three](https://daily.dev/posts/we-thought-chinese-companies-could-save-us-from-the-dram-crisis-but-they-re-charging-just-as-much-a-wdezvmkqr) · XDA Developers · 0 upvotes · 0 comments --- Tags: [#samsung](https://daily.dev/tags/samsung) [View this post on daily.dev](https://daily.dev/posts/why-micron-is-suddenly-ditching-4f-dram-as-rivals-double-down-4haigbuoi) ```json {"@context":"https://schema.org","@graph":[{"@type":"Organization","@id":"https://daily.dev/#organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180},"sameAs":["https://twitter.com/dailydotdev","https://github.com/dailydotdev","https://www.linkedin.com/company/daily-dev-ltd"]},{"@type":"WebSite","@id":"https://daily.dev/#website","url":"https://daily.dev","name":"daily.dev","publisher":{"@id":"https://daily.dev/#organization"},"potentialAction":{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https://daily.dev/search?q={search_term_string}"},"query-input":"required name=search_term_string"}}]} {"@context":"https://schema.org","@type":"TechArticle","headline":"Why Micron Is Suddenly Ditching 4F² DRAM as Rivals Double Down","url":"https://daily.dev/posts/why-micron-is-suddenly-ditching-4f-dram-as-rivals-double-down-4haigbuoi","mainEntityOfPage":{"@type":"WebPage","@id":"https://daily.dev/posts/why-micron-is-suddenly-ditching-4f-dram-as-rivals-double-down-4haigbuoi"},"datePublished":"2026-10-27T16:30:07.877Z","dateModified":"2026-10-27T22:32:46.487Z","description":"Micron is abandoning 4F² DRAM cell geometry after more than two decades of research, choosing to stick with 6F² instead. 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