--- title: FPGA News & Updates | daily.dev description: FPGA news and updates covering field-programmable gate arrays, chips whose logic is configured after manufacture. Readers can learn about hardware description languages such as Verilog and VHDL, synthesis and timing closure, open-source and vendor toolchains, and use in prototyping. canonical: https://daily.dev/tags/fpga twitter:card: summary_large_image twitter:site: @dailydotdev og:url: https://daily.dev/tags/fpga og:type: website og:site_name: daily.dev og:title: FPGA News & Updates | daily.dev og:description: FPGA news and updates covering field-programmable gate arrays, chips whose logic is configured after manufacture. Readers can learn about hardware description languages such as Verilog and VHDL, synthesis and timing closure, open-source and vendor toolchains, and use in prototyping. og:image: https://api.daily.dev/og/tags/fpga.png og:image:width: 1200 og:image:height: 630 --- ## Recommended FPGA stories ## Who to follow for FPGA [](https://daily.dev/cnxsoft) [CNXSoft](https://daily.dev/cnxsoft) [@cnxsoft](https://daily.dev/cnxsoft) Joined Feb 18\. 2022 350 ## Top sources covering FPGA ## Most upvoted FPGA posts ## Best discussed FPGA posts ## All posts about FPGA ```json {"@context":"https://schema.org","@graph":[{"@type":"Organization","@id":"https://daily.dev/#organization","name":"daily.dev","url":"https://daily.dev","logo":{"@type":"ImageObject","url":"https://daily.dev/apple-touch-icon.png","width":180,"height":180},"sameAs":["https://twitter.com/dailydotdev","https://github.com/dailydotdev","https://www.linkedin.com/company/daily-dev-ltd"]},{"@type":"WebSite","@id":"https://daily.dev/#website","url":"https://daily.dev","name":"daily.dev","publisher":{"@id":"https://daily.dev/#organization"},"potentialAction":{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https://daily.dev/search?q={search_term_string}"},"query-input":"required name=search_term_string"}}]} {"@context":"https://schema.org","@graph":[{"@type":"CollectionPage","@id":"https://daily.dev/tags/fpga#page","url":"https://daily.dev/tags/fpga","name":"FPGA News & Updates","description":"FPGA news and updates covering field-programmable gate arrays, chips whose logic is configured after manufacture. Readers can learn about hardware description languages such as Verilog and VHDL, synthesis and timing closure, open-source and vendor toolchains, and use in prototyping.","isPartOf":{"@type":"WebSite","url":"https://daily.dev"}},{"@type":"ItemList","@id":"https://daily.dev/tags/fpga#items","numberOfItems":10,"itemListElement":[{"@type":"ListItem","position":1,"url":"https://daily.dev/posts/turingmotors-swan-this-project-aims-to-enable-language-model-inference-on-fpgas-supporting-ai-appl-lamuzeyqc","name":"turingmotors/swan: This project aims to enable language model inference on FPGAs, supporting AI applications in edge devices and environments with limited resources."},{"@type":"ListItem","position":2,"url":"https://daily.dev/posts/microzed-chronicles-linear-feedback-shift-register-9aqdtoj4s","name":"MicroZed Chronicles: Linear Feedback Shift Register"},{"@type":"ListItem","position":3,"url":"https://daily.dev/posts/zeroasiccorp-logik-a-configurable-rtl-to-bitstream-fpga-toolchain-cc3fahkkp","name":"zeroasiccorp/logik: A configurable RTL to bitstream FPGA toolchain"},{"@type":"ListItem","position":4,"url":"https://daily.dev/posts/stopwatch-implementation-on-fpga-board-oui1puor7","name":"Stopwatch implementation on FPGA board"},{"@type":"ListItem","position":5,"url":"https://daily.dev/posts/furygpu-wfv6onbho","name":"FuryGpu"},{"@type":"ListItem","position":6,"url":"https://daily.dev/posts/efinix-titanium-ti375-fpga-offers-quad-core-hardened-risc-v-block-pcie-gen-4-10gbe-6bdlijo8y","name":"Efinix Titanium Ti375 FPGA offers quad-core hardened RISC-V block, PCIe Gen 4, 10GbE"},{"@type":"ListItem","position":7,"url":"https://daily.dev/posts/the-results-of-7-verilog-meetups-the-goals-and-the-steps-going-forward-ezbvarznf","name":"The results of 7 Verilog meetups + the goals and the steps going forward"},{"@type":"ListItem","position":8,"url":"https://daily.dev/posts/amd-introduces-spartan-ultrascale-programmable-logic-chips-for-edge-applications-ssqbojseg","name":"AMD introduces Spartan UltraScale+ programmable logic chips for edge applications"},{"@type":"ListItem","position":9,"url":"https://daily.dev/posts/bootstrapping-azerbaijan-as-a-new-center-of-asic-design-verilog-meetup-6-in-silicon-valley-fg3w0kvti","name":"Bootstrapping Azerbaijan as a new center of ASIC design + Verilog Meetup #6 in Silicon Valley"},{"@type":"ListItem","position":10,"url":"https://daily.dev/posts/openfpga-8l13ujnum","name":"openFPGA"}]},{"@type":"BreadcrumbList","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https://daily.dev"},{"@type":"ListItem","position":2,"name":"Tags","item":"https://daily.dev/tags"},{"@type":"ListItem","position":3,"name":"FPGA"}]}]} ```