An absolute position encoder VHDL core

A VHDL core called 'absenc' was developed to unify multiple absolute position encoder interfaces (ENDAT, BISS, SSI) for FPGA-based motion control systems. The core supports both master and slave roles, allows runtime selection of the active interface, and shares hardware resources across interfaces to remain resource-efficient. Motivated by redundant implementations at the ESRF synchrotron facility, the design is extensible for future interfaces. The project is open-sourced on CERN OHWR and mirrored on GitHub.