Fixed-point fractional arithmetic is error-prone, especially around overflow behavior and binary-point tracking. Unlike integer overflow (losing MSBs), fractional overflow loses LSBs. Q notation helps track scaling throughout an algorithm. When multiplying signed fixed-point values, extra sign bits appear in the result, requiring careful handling. Three strategies for managing bit growth in FPGA implementations are discussed: keeping all bits (resource-heavy), shifting selectively (near floating-point complexity), or normalizing aggressively after each operation (simpler but less precise). Practical advice includes validating fixed-point intermediate values against floating-point references and aligning results to FPGA memory widths (typically multiples of 8 or 16 bits).
